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Match X86 register names to number.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77404 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -410,6 +410,27 @@ def COPY_TO_REGCLASS : Instruction {
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let isAsCheapAsAMove = 1;
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}
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//===----------------------------------------------------------------------===//
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// AsmParser - This class can be implemented by targets that wish to implement
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// .s file parsing.
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//
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// Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
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// syntax on X86 for example).
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//
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class AsmParser {
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// AsmWriterClassName - This specifies the suffix to use for the asmwriter
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// class. Generated AsmWriter classes are always prefixed with the target
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// name.
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string AsmParserClassName = "AsmParser";
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// Variant - AsmParsers can be of multiple different variants. Variants are
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// used to support targets that need to parser multiple formats for the
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// assembly language.
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int Variant = 0;
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}
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def DefaultAsmParser : AsmParser;
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//===----------------------------------------------------------------------===//
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// AsmWriter - This class can be implemented by targets that need to customize
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// the format of the .s file writer.
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@ -445,6 +466,9 @@ class Target {
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// InstructionSet - Instruction set description for this target.
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InstrInfo InstructionSet;
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// AssemblyParsers - The AsmParser instances available for this target.
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list<AsmParser> AssemblyParsers = [DefaultAsmParser];
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// AssemblyWriters - The AsmWriter instances available for this target.
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list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
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}
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@ -42,6 +42,13 @@ private:
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bool ParseOperand(X86Operand &Op);
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bool ParseMemOperand(X86Operand &Op);
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/// @name Auto-generated Match Functions
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/// {
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bool MatchRegisterName(const StringRef &Name, unsigned &RegNo);
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/// }
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public:
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X86ATTAsmParser(const Target &T, MCAsmParser &_Parser)
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@ -118,10 +125,17 @@ struct X86Operand {
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//
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bool X86ATTAsmParser::ParseRegister(X86Operand &Op) {
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assert(getLexer().is(AsmToken::Register) && "Invalid token kind!");
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AsmToken Tok = getLexer().getTok();
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assert(Tok.is(AsmToken::Register) && "Invalid token kind!");
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// FIXME: Decode register number.
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Op = X86Operand::CreateReg(123);
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// FIXME: Validate register for the current architecture; we have to do
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// validation later, so maybe there is no need for this here.
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unsigned RegNo;
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assert(Tok.getString().startswith("%") && "Invalid register name!");
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if (MatchRegisterName(Tok.getString().substr(1), RegNo))
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return Error(Tok.getLoc(), "invalid register name");
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Op = X86Operand::CreateReg(RegNo);
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getLexer().Lex(); // Eat register token.
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return false;
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@ -308,3 +322,5 @@ extern "C" void LLVMInitializeX86AsmParser() {
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RegisterAsmParser<X86ATTAsmParser> X(TheX86_32Target);
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RegisterAsmParser<X86ATTAsmParser> Y(TheX86_64Target);
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}
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#include "X86GenAsmMatcher.inc"
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@ -178,6 +178,12 @@ include "X86CallingConv.td"
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// Assembly Printers
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//===----------------------------------------------------------------------===//
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// Currently the X86 assembly parser only supports ATT syntax.
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def ATTAsmParser : AsmParser {
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string AsmParserClassName = "ATTAsmParser";
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int Variant = 0;
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}
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// The X86 target supports two different syntaxes for emitting machine code.
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// This is controlled by the -x86-asm-syntax={att|intel}
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def ATTAsmWriter : AsmWriter {
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@ -189,10 +195,11 @@ def IntelAsmWriter : AsmWriter {
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int Variant = 1;
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}
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def X86 : Target {
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// Information about the instructions...
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let InstructionSet = X86InstrInfo;
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let AssemblyParsers = [ATTAsmParser];
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let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
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}
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@ -20,17 +20,17 @@ using namespace llvm;
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void AsmMatcherEmitter::run(raw_ostream &OS) {
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CodeGenTarget Target;
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const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
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Record *AsmParser = Target.getAsmParser();
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std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
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std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace");
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EmitSourceFileHeader("Assembly Matcher Source Fragment", OS);
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OS << "namespace llvm {\n\n";
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// Emit the function to match a register name to number.
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if (!Namespace.empty())
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OS << "namespace " << Namespace << " {\n";
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OS << "bool MatchRegisterName(const std::string &Name, unsigned &RegNo) {\n";
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OS << "bool " << Target.getName() << ClassName
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<< "::MatchRegisterName(const StringRef &Name, unsigned &RegNo) {\n";
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// FIXME: TableGen should have a fast string matcher generator.
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for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
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@ -44,8 +44,4 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
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}
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OS << " return true;\n";
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OS << "}\n";
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if (!Namespace.empty())
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OS << "}\n";
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OS << "} // End llvm namespace \n";
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}
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@ -22,6 +22,10 @@
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#include <algorithm>
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using namespace llvm;
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static cl::opt<unsigned>
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AsmParserNum("asmparsernum", cl::init(0),
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cl::desc("Make -gen-asm-parser emit assembly parser #N"));
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static cl::opt<unsigned>
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AsmWriterNum("asmwriternum", cl::init(0),
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cl::desc("Make -gen-asm-writer emit assembly writer #N"));
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@ -133,6 +137,15 @@ Record *CodeGenTarget::getInstructionSet() const {
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return TargetRec->getValueAsDef("InstructionSet");
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}
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/// getAsmParser - Return the AssemblyParser definition for this target.
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///
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Record *CodeGenTarget::getAsmParser() const {
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std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers");
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if (AsmParserNum >= LI.size())
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throw "Target does not have an AsmParser #" + utostr(AsmParserNum) + "!";
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return LI[AsmParserNum];
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}
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/// getAsmWriter - Return the AssemblyWriter definition for this target.
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///
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Record *CodeGenTarget::getAsmWriter() const {
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@ -87,6 +87,10 @@ public:
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///
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Record *getInstructionSet() const;
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/// getAsmParser - Return the AssemblyParser definition for this target.
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///
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Record *getAsmParser() const;
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/// getAsmWriter - Return the AssemblyWriter definition for this target.
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///
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Record *getAsmWriter() const;
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