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Convert bytes to bits in alignment

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15971 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2004-08-21 20:09:46 +00:00
parent 7008034c9f
commit 0e362770d0
2 changed files with 6 additions and 6 deletions
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6
lib/Target/Sparc/SparcRegisterInfo.td
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@ -71,7 +71,7 @@ let Namespace = "V8" in {
// FIXME: the register order should be defined in terms of the preferred
// allocation order...
//
def IntRegs : RegisterClass<i32, 8, [L0, L1, L2, L3, L4, L5, L6, L7,
def IntRegs : RegisterClass<i32, 64, [L0, L1, L2, L3, L4, L5, L6, L7,
I0, I1, I2, I3, I4, I5,
G1, G2, G3, G4, G5, G6, G7,
O0, O1, O2, O3, O4, O5, O7,
@ -84,11 +84,11 @@ def IntRegs : RegisterClass<i32, 8, [L0, L1, L2, L3, L4, L5, L6, L7,
}];
}
def FPRegs : RegisterClass<f32, 4, [F0, F1, F2, F3, F4, F5, F6, F7, F8,
def FPRegs : RegisterClass<f32, 32, [F0, F1, F2, F3, F4, F5, F6, F7, F8,
F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22,
F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
def DFPRegs : RegisterClass<f64, 8, [D0, D1, D2, D3, D4, D5, D6, D7,
def DFPRegs : RegisterClass<f64, 64, [D0, D1, D2, D3, D4, D5, D6, D7,
D8, D9, D10, D11, D12, D13, D14, D15]>;
// Tell the register file generator that the double-fp pseudo-registers

6
lib/Target/SparcV8/SparcV8RegisterInfo.td
View File

@ -71,7 +71,7 @@ let Namespace = "V8" in {
// FIXME: the register order should be defined in terms of the preferred
// allocation order...
//
def IntRegs : RegisterClass<i32, 8, [L0, L1, L2, L3, L4, L5, L6, L7,
def IntRegs : RegisterClass<i32, 64, [L0, L1, L2, L3, L4, L5, L6, L7,
I0, I1, I2, I3, I4, I5,
G1, G2, G3, G4, G5, G6, G7,
O0, O1, O2, O3, O4, O5, O7,
@ -84,11 +84,11 @@ def IntRegs : RegisterClass<i32, 8, [L0, L1, L2, L3, L4, L5, L6, L7,
}];
}
def FPRegs : RegisterClass<f32, 4, [F0, F1, F2, F3, F4, F5, F6, F7, F8,
def FPRegs : RegisterClass<f32, 32, [F0, F1, F2, F3, F4, F5, F6, F7, F8,
F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22,
F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
def DFPRegs : RegisterClass<f64, 8, [D0, D1, D2, D3, D4, D5, D6, D7,
def DFPRegs : RegisterClass<f64, 64, [D0, D1, D2, D3, D4, D5, D6, D7,
D8, D9, D10, D11, D12, D13, D14, D15]>;
// Tell the register file generator that the double-fp pseudo-registers