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Kill a majority of unnecessary sign extensions for byte loads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15991 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -32,9 +32,6 @@
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using namespace llvm;
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namespace {
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Statistic<> GEPFolds("ppc-codegen", "Number of GEPs folded");
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Statistic<> NumSetCC("ppc-codegen", "Number of SetCC straight-lined");
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/// TypeClass - Used by the PowerPC backend to group LLVM types by their basic
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/// PPC Representation.
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///
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@ -283,7 +280,7 @@ namespace {
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unsigned ExtendOrClear(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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unsigned Reg, const Type *CompTy);
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Value *Op0, Value *Op1);
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/// promote32 - Make a value 32-bits wide, and put it somewhere.
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///
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@ -917,13 +914,11 @@ static GetElementPtrInst *canFoldGEPIntoLoadOrStore(Value *V) {
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GEPI->getParent() == User->getParent() &&
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User->getOperand(0) != GEPI &&
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User->getOperand(1) == GEPI) {
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++GEPFolds;
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return GEPI;
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}
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if (isa<LoadInst>(User) &&
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GEPI->getParent() == User->getParent() &&
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User->getOperand(0) == GEPI) {
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++GEPFolds;
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return GEPI;
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}
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}
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@ -966,7 +961,9 @@ void ISel::emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
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unsigned ISel::ExtendOrClear(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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unsigned Reg, const Type *CompTy) {
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Value *Op0, Value *Op1) {
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const Type *CompTy = Op0->getType();
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unsigned Reg = getReg(Op0, MBB, IP);
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unsigned Class = getClassB(CompTy);
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// Before we do a comparison or SetCC, we have to make sure that we truncate
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@ -1000,7 +997,7 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
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// The arguments are already supposed to be of the same type.
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const Type *CompTy = Op0->getType();
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unsigned Class = getClassB(CompTy);
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unsigned Op0r = ExtendOrClear(MBB, IP, getReg(Op0, MBB, IP), CompTy);
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unsigned Op0r = ExtendOrClear(MBB, IP, Op0, Op1);
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// Use crand for lt, gt and crandc for le, ge
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unsigned CROpcode = (OpNum == 2 || OpNum == 4) ? PPC::CRAND : PPC::CRANDC;
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@ -2384,6 +2381,27 @@ void ISel::emitShiftOperation(MachineBasicBlock *MBB,
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}
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}
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/// LoadNeedsSignExtend - On PowerPC, there is no load byte with sign extend.
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/// Therefore, if this is a byte load and the destination type is signed, we
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/// would normall need to also emit a sign extend instruction after the load.
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/// However, store instructions don't care whether a signed type was sign
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/// extended across a whole register. Also, a SetCC instruction will emit its
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/// own sign extension to force the value into the appropriate range, so we
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/// need not emit it here. Ideally, this kind of thing wouldn't be necessary
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/// once LLVM's type system is improved.
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static bool LoadNeedsSignExtend(LoadInst &LI) {
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if (cByte == getClassB(LI.getType()) && LI.getType()->isSigned()) {
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bool AllUsesAreStoresOrSetCC = true;
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for (Value::use_iterator I = LI.use_begin(), E = LI.use_end(); I != E; ++I)
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if (!isa<StoreInst>(*I) && !isa<SetCondInst>(*I)) {
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AllUsesAreStoresOrSetCC = false;
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break;
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}
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if (!AllUsesAreStoresOrSetCC)
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return true;
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}
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return false;
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}
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/// visitLoadInst - Implement LLVM load instructions. Pretty straightforward
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/// mapping of LLVM classes to PPC load instructions, with the exception of
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@ -2415,7 +2433,7 @@ void ISel::visitLoadInst(LoadInst &I) {
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if (Class == cLong) {
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addFrameReference(BuildMI(BB, ImmOpcode, 2, DestReg), FI);
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addFrameReference(BuildMI(BB, ImmOpcode, 2, DestReg+1), FI, 4);
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} else if (Class == cByte && I.getType()->isSigned()) {
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} else if (LoadNeedsSignExtend(I)) {
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unsigned TmpReg = makeAnotherReg(I.getType());
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addFrameReference(BuildMI(BB, ImmOpcode, 2, TmpReg), FI);
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BuildMI(BB, PPC::EXTSB, 1, DestReg).addReg(TmpReg);
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@ -2441,7 +2459,7 @@ void ISel::visitLoadInst(LoadInst &I) {
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if (pendingAdd == 0 && Class != cLong &&
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canUseAsImmediateForOpcode(offset, 0)) {
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if (Class == cByte && I.getType()->isSigned()) {
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if (LoadNeedsSignExtend(I)) {
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unsigned TmpReg = makeAnotherReg(I.getType());
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BuildMI(BB, ImmOpcode, 2, TmpReg).addSImm(offset->getValue())
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.addReg(baseReg);
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@ -2460,7 +2478,7 @@ void ISel::visitLoadInst(LoadInst &I) {
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BuildMI(BB, PPC::ADDI, 2, indexPlus4).addReg(indexReg).addSImm(4);
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BuildMI(BB, IdxOpcode, 2, DestReg).addReg(indexReg).addReg(baseReg);
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BuildMI(BB, IdxOpcode, 2, DestReg+1).addReg(indexPlus4).addReg(baseReg);
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} else if (Class == cByte && I.getType()->isSigned()) {
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} else if (LoadNeedsSignExtend(I)) {
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unsigned TmpReg = makeAnotherReg(I.getType());
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BuildMI(BB, IdxOpcode, 2, TmpReg).addReg(indexReg).addReg(baseReg);
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BuildMI(BB, PPC::EXTSB, 1, DestReg).addReg(TmpReg);
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@ -2477,7 +2495,7 @@ void ISel::visitLoadInst(LoadInst &I) {
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if (Class == cLong) {
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BuildMI(BB, ImmOpcode, 2, DestReg).addSImm(0).addReg(SrcAddrReg);
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BuildMI(BB, ImmOpcode, 2, DestReg+1).addSImm(4).addReg(SrcAddrReg);
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} else if (Class == cByte && I.getType()->isSigned()) {
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} else if (LoadNeedsSignExtend(I)) {
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unsigned TmpReg = makeAnotherReg(I.getType());
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BuildMI(BB, ImmOpcode, 2, TmpReg).addSImm(0).addReg(SrcAddrReg);
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BuildMI(BB, PPC::EXTSB, 1, DestReg).addReg(TmpReg);
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