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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-18 12:29:21 +00:00
Fix some brittle code. Watch out for cases where register scavenger is pointing to deleted instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34998 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -40,6 +40,7 @@ namespace {
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const TargetInstrInfo *TII;
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const MRegisterInfo *MRI;
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RegScavenger *RS;
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MachineBasicBlock::iterator RSI;
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virtual bool runOnMachineFunction(MachineFunction &Fn);
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@ -59,11 +60,10 @@ namespace {
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typedef SmallVector<MemOpQueueEntry,8> MemOpQueue;
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typedef MemOpQueue::iterator MemOpQueueIter;
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void AdvanceRS(MachineBasicBlock *MBB, MemOpQueue &MemOps);
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SmallVector<MachineBasicBlock::iterator, 4>
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MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex, unsigned Base,
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int Opcode, unsigned Size, MemOpQueue &MemOps);
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int Opcode, unsigned Size, unsigned Scratch,
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MemOpQueue &MemOps);
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bool LoadStoreMultipleOpti(MachineBasicBlock &MBB);
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bool MergeReturnIntoLDM(MachineBasicBlock &MBB);
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@ -106,8 +106,8 @@ static int getLoadStoreMultipleOpcode(int Opcode) {
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/// It returns true if the transformation is done.
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static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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int Offset, unsigned Base, bool BaseKill, int Opcode,
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unsigned Scratch,
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SmallVector<std::pair<unsigned, bool>, 8> &Regs,
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RegScavenger *RS,
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const TargetInstrInfo *TII) {
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// Only a single register to load / store. Don't bother.
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unsigned NumRegs = Regs.size();
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@ -135,8 +135,8 @@ static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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// use as the new base.
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NewBase = Regs[NumRegs-1].first;
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else {
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// Try to find a free register to use as a new base.
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NewBase = RS ? RS->FindUnusedReg(&ARM::GPRRegClass) : (unsigned)ARM::R12;
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// Use the scratch register to use as a new base.
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NewBase = Scratch;
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if (NewBase == 0)
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return false;
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}
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@ -169,31 +169,12 @@ static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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return true;
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}
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/// AdvanceRS - Advance register scavenger to just before the earliest memory
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/// op that is being merged.
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void ARMLoadStoreOpt::AdvanceRS(MachineBasicBlock *MBB, MemOpQueue &MemOps) {
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MachineBasicBlock::iterator Loc = MemOps[0].MBBI;
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unsigned Position = MemOps[0].Position;
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for (unsigned i = 1, e = MemOps.size(); i != e; ++i) {
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if (MemOps[i].Position < Position) {
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Position = MemOps[i].Position;
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Loc = MemOps[i].MBBI;
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}
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}
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if (Loc != MBB->begin())
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RS->forward(prior(Loc));
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}
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/// MergeLDR_STR - Merge a number of load / store instructions into one or more
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/// load / store multiple instructions.
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SmallVector<MachineBasicBlock::iterator, 4>
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ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB,
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unsigned SIndex, unsigned Base, int Opcode,
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unsigned Size, MemOpQueue &MemOps) {
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if (RS && SIndex == 0)
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AdvanceRS(&MBB, MemOps);
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ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
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unsigned Base, int Opcode, unsigned Size,
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unsigned Scratch, MemOpQueue &MemOps) {
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SmallVector<MachineBasicBlock::iterator, 4> Merges;
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SmallVector<std::pair<unsigned,bool>, 8> Regs;
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bool isAM4 = Opcode == ARM::LDR || Opcode == ARM::STR;
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@ -219,7 +200,7 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB,
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PRegNum = RegNum;
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} else {
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// Can't merge this in. Try merge the earlier ones first.
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if (mergeOps(MBB, ++Loc, SOffset, Base, false, Opcode, Regs, RS, TII)) {
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if (mergeOps(MBB, ++Loc, SOffset, Base, false, Opcode,Scratch,Regs,TII)) {
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Merges.push_back(prior(Loc));
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for (unsigned j = SIndex; j < i; ++j) {
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MBB.erase(MemOps[j].MBBI);
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@ -227,7 +208,7 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB,
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}
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}
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SmallVector<MachineBasicBlock::iterator, 4> Merges2 =
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MergeLDR_STR(MBB, i, Base, Opcode, Size, MemOps);
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MergeLDR_STR(MBB, i, Base, Opcode, Size, Scratch, MemOps);
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Merges.append(Merges2.begin(), Merges2.end());
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return Merges;
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}
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@ -239,7 +220,7 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB,
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}
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bool BaseKill = Loc->findRegisterUseOperand(Base, true) != NULL;
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if (mergeOps(MBB, ++Loc, SOffset, Base, BaseKill, Opcode, Regs, RS, TII)) {
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if (mergeOps(MBB, ++Loc, SOffset, Base, BaseKill, Opcode,Scratch,Regs, TII)) {
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Merges.push_back(prior(Loc));
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for (unsigned i = SIndex, e = MemOps.size(); i != e; ++i) {
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MBB.erase(MemOps[i].MBBI);
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@ -520,7 +501,8 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
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unsigned CurrSize = 0;
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unsigned Position = 0;
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if (RS) RS->enterBasicBlock(&MBB);
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RS->enterBasicBlock(&MBB);
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RSI = MBB.begin();
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MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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while (MBBI != E) {
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bool Advance = false;
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@ -600,22 +582,38 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
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if (TryMerge) {
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if (NumMemOps > 1) {
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// Try to find a free register to use as a new base in case it's needed.
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unsigned Scratch = ARM::R12;
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// First advance to the instruction just before the start of the chain.
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if (RSI != MBB.begin())
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RS->forward(prior(RSI));
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// Find a scratch register.
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Scratch = RS->FindUnusedReg(&ARM::GPRRegClass);
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// Process the load / store instructions.
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RS->forward(prior(MBBI));
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// Merge ops.
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SmallVector<MachineBasicBlock::iterator,4> MBBII =
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MergeLDR_STR(MBB, 0, CurrBase, CurrOpc, CurrSize, MemOps);
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MergeLDR_STR(MBB, 0, CurrBase, CurrOpc, CurrSize, Scratch, MemOps);
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// Try folding preceeding/trailing base inc/dec into the generated
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// LDM/STM ops.
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for (unsigned i = 0, e = MBBII.size(); i < e; ++i)
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if (mergeBaseUpdateLSMultiple(MBB, MBBII[i]))
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NumMerges++;
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NumMerges += MBBII.size();
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}
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// Try folding preceeding/trailing base inc/dec into those load/store
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// that were not merged to form LDM/STM ops.
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for (unsigned i = 0; i != NumMemOps; ++i)
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if (!MemOps[i].Merged)
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if (mergeBaseUpdateLoadStore(MBB, MemOps[i].MBBI, TII))
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NumMerges++;
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// Try folding preceeding/trailing base inc/dec into those load/store
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// that were not merged to form LDM/STM ops.
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for (unsigned i = 0; i != NumMemOps; ++i)
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if (!MemOps[i].Merged)
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if (mergeBaseUpdateLoadStore(MBB, MemOps[i].MBBI, TII))
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NumMerges++;
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// RS may be pointing to an instruction that's deleted.
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RS->skipTo(prior(MBBI));
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RSI = MBBI;
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}
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CurrBase = 0;
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CurrOpc = -1;
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@ -665,7 +663,7 @@ bool ARMLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
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const TargetMachine &TM = Fn.getTarget();
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TII = TM.getInstrInfo();
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MRI = TM.getRegisterInfo();
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RS = MRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : NULL;
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RS = new RegScavenger();
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bool Modified = false;
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for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
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