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Convert all of the DForm_6* operations, which makes all of the Zimm16 users
dead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15754 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -89,6 +89,8 @@ namespace {
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if (MO.getType() == MachineOperand::MO_MachineRegister) {
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assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
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O << LowercaseString(TM.getRegisterInfo()->get(MO.getReg()).Name);
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} else if (MO.isImmediate()) {
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O << MO.getImmedValue();
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} else {
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printOp(MO);
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}
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@ -89,6 +89,8 @@ namespace {
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if (MO.getType() == MachineOperand::MO_MachineRegister) {
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assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
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O << LowercaseString(TM.getRegisterInfo()->get(MO.getReg()).Name);
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} else if (MO.isImmediate()) {
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O << MO.getImmedValue();
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} else {
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printOp(MO);
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}
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@ -18,7 +18,6 @@ def Pseudo: Format<0>;
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def Gpr : Format<1>;
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def Gpr0 : Format<2>;
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def Simm16 : Format<3>;
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def Zimm16 : Format<4>;
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def PCRelimm24 : Format<5>;
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def Imm24 : Format<6>;
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def Imm5 : Format<7>;
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@ -152,8 +151,8 @@ class DForm_4<bits<6> opcode, bit ppc64, bit vmx,
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let AsmString = asmstr;
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}
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class DForm_4_zero<string name, bits<6> opcode, bit ppc64, bit vmx>
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: DForm_1<name, opcode, ppc64, vmx> {
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class DForm_4_zero<string name, bits<6> opcode, bit ppc64, bit vmx,
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dag OL, string asmstr> : DForm_1<"", opcode, ppc64, vmx> {
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let ArgCount = 0;
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let Arg0Type = 0;
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let Arg1Type = 0;
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@ -161,6 +160,8 @@ class DForm_4_zero<string name, bits<6> opcode, bit ppc64, bit vmx>
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let A = 0;
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let B = 0;
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let C = 0;
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let OperandList = OL;
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let AsmString = asmstr;
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}
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class DForm_5<string name, bits<6> opcode, bit ppc64, bit vmx>
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@ -194,13 +195,16 @@ class DForm_5_ext<string name, bits<6> opcode, bit ppc64, bit vmx>
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let Arg3Type = 0;
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}
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class DForm_6<string name, bits<6> opcode, bit ppc64, bit vmx>
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: DForm_5<name, opcode, ppc64, vmx> {
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let Arg3Type = Zimm16.Value;
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class DForm_6<bits<6> opcode, bit ppc64, bit vmx,
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dag OL, string asmstr>
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: DForm_5<"", opcode, ppc64, vmx> {
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let OperandList = OL;
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let AsmString = asmstr;
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}
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class DForm_6_ext<string name, bits<6> opcode, bit ppc64, bit vmx>
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: DForm_6<name, opcode, ppc64, vmx> {
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class DForm_6_ext<bits<6> opcode, bit ppc64, bit vmx,
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dag OL, string asmstr>
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: DForm_6<opcode, ppc64, vmx, OL, asmstr> {
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let L = ppc64;
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let ArgCount = 3;
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let Arg0Type = Imm3.Value;
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@ -85,9 +85,15 @@ def CMPDI : DForm_5_ext<"cmpdi", 11, 1, 0>;
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def CMP : XForm_16<"cmp", 31, 0, 0, 0>;
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def CMPW : XForm_16_ext<"cmpw", 31, 0, 0, 0>;
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def CMPD : XForm_16_ext<"cmpd", 31, 0, 1, 0>;
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def CMPLI : DForm_6<"cmpli", 10, 0, 0>;
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def CMPLWI : DForm_6_ext<"cmplwi", 10, 0, 0>;
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def CMPLDI : DForm_6_ext<"cmpldi", 10, 1, 0>;
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def CMPLI : DForm_6<10, 0, 0,
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(ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
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"cmpli $dst, $size, $src1, $src2">;
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def CMPLWI : DForm_6_ext<10, 0, 0,
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(ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
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"cmplwi $dst, $src1, $src2">;
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def CMPLDI : DForm_6_ext<10, 1, 0,
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(ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
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"cmpldi $dst, $src1, $src2">;
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def CMPL : XForm_16<"cmpl", 31, 32, 0, 0>;
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def CMPLW : XForm_16_ext<"cmplw", 31, 32, 0, 0>;
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def CMPLD : XForm_16_ext<"cmpld", 31, 32, 1, 0>;
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@ -144,7 +150,7 @@ def MULHWU : XOForm_2<"mulhwu", 31, 11, 0, 0, 0>;
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def NAND : XForm_6<"nand", 31, 476, 0, 0, 0>;
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def NEG : XOForm_3<"neg", 31, 104, 0, 0, 0, 0>;
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def NOR : XForm_6<"nor", 31, 124, 0, 0, 0>;
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def NOP : DForm_4_zero<"nop", 24, 0, 0>;
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def NOP : DForm_4_zero<"nop", 24, 0, 0, (ops), "nop">;
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def ORI : DForm_4<24, 0, 0,
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(ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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"ori $dst, $src1, $src2">;
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