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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 02:29:22 +00:00
Add some 64-bit logical ops.
Split imm16Shifted into a sext/zext form for 64-bit support.
Add some patterns for immediate formation. For example, we now compile this:
static unsigned long long Y;
void test3() {
Y = 0xF0F00F00;
}
into:
_test3:
li r2, 3840
lis r3, ha16(_Y)
xoris r2, r2, 61680
std r2, lo16(_Y)(r3)
blr
GCC produces:
_test3:
li r0,0
lis r2,ha16(_Y)
ori r0,r0,61680
sldi r0,r0,16
ori r0,r0,3840
std r0,lo16(_Y)(r2)
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28883 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
cf9be26e5d
commit
0ea70b219a
@ -31,13 +31,7 @@ def symbolLo64 : Operand<i64> {
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let PPC970_Unit = 1 in { // FXU Operations.
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def LI8 : DForm_2_r0<14, (ops G8RC:$rD, symbolLo64:$imm),
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"li $rD, $imm", IntGeneral,
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[(set G8RC:$rD, immSExt16:$imm)]>;
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def LIS8 : DForm_2_r0<15, (ops G8RC:$rD, symbolHi64:$imm),
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"lis $rD, $imm", IntGeneral,
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[(set G8RC:$rD, imm16Shifted:$imm)]>;
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// Copies, extends, truncates.
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def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
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"or $rA, $rS, $rB", IntGeneral,
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[(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
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@ -47,13 +41,47 @@ def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
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def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
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"or $rA, $rS, $rB", IntGeneral,
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[]>;
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def LI8 : DForm_2_r0<14, (ops G8RC:$rD, symbolLo64:$imm),
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"li $rD, $imm", IntGeneral,
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[(set G8RC:$rD, immSExt16:$imm)]>;
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def LIS8 : DForm_2_r0<15, (ops G8RC:$rD, symbolHi64:$imm),
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"lis $rD, $imm", IntGeneral,
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[(set G8RC:$rD, imm16ShiftedSExt:$imm)]>;
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// Logical ops.
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def ANDIo8 : DForm_4<28, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
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"andi. $dst, $src1, $src2", IntGeneral,
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[(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>,
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isDOT;
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def ANDISo8 : DForm_4<29, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
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"andis. $dst, $src1, $src2", IntGeneral,
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[(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>,
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isDOT;
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def ORI8 : DForm_4<24, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
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"ori $dst, $src1, $src2", IntGeneral,
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[(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>;
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def ORIS8 : DForm_4<25, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
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"oris $dst, $src1, $src2", IntGeneral,
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[(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>;
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def XORI8 : DForm_4<26, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
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"xori $dst, $src1, $src2", IntGeneral,
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[(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>;
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def XORIS8 : DForm_4<27, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
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"xoris $dst, $src1, $src2", IntGeneral,
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[(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>;
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def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
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"add $rT, $rA, $rB", IntGeneral,
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[(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
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def ADDIS8 : DForm_2<15, (ops G8RC:$rD, G8RC:$rA, symbolHi64:$imm),
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"addis $rD, $rA, $imm", IntGeneral,
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[(set G8RC:$rD, (add G8RC:$rA, imm16Shifted:$imm))]>;
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[(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>;
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def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
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"mulhd $rT, $rA, $rB", IntMulHW,
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@ -186,6 +214,28 @@ def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
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//===----------------------------------------------------------------------===//
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// Instruction Patterns
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//
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// Immediate support.
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// Handled above:
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// sext(0x0000_0000_0000_FFFF, i8) -> li imm
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// sext(0x0000_0000_FFFF_0000, i16) -> lis imm>>16
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// sext(0x0000_0000_FFFF_FFFF, i16) -> lis + ori
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def sext_0x0000_0000_FFFF_FFFF_i16 : PatLeaf<(imm), [{
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return N->getValue() == (uint64_t)(int32_t)N->getValue();
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}]>;
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def : Pat<(i64 sext_0x0000_0000_FFFF_FFFF_i16:$imm),
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(ORI8 (LIS8 (HI16 imm:$imm)), (LO16 imm:$imm))>;
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// zext(0x0000_0000_FFFF_FFFF, i16) -> xoris (li lo16(imm)), imm>>16
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def zext_0x0000_0000_FFFF_FFFF_i16 : PatLeaf<(imm), [{
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return (N->getValue() & 0xFFFFFFFF00000000ULL) == 0;
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}]>;
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def : Pat<(i64 zext_0x0000_0000_FFFF_FFFF_i16:$imm),
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(XORIS8 (LI8 (LO16 imm:$imm)), (HI16 imm:$imm))>;
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// Extensions and truncates to/from 32-bit regs.
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def : Pat<(i64 (zext GPRC:$in)),
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(RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
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@ -140,9 +140,21 @@ def immZExt16 : PatLeaf<(imm), [{
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return (unsigned)N->getValue() == (unsigned short)N->getValue();
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}], LO16>;
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def imm16Shifted : PatLeaf<(imm), [{
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// imm16Shifted predicate - True if only bits in the top 16-bits of the
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// immediate are set. Used by instructions like 'addis'.
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// imm16Shifted* - These match immediates where the low 16-bits are zero. There
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// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
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// identical in 32-bit mode, but in 64-bit mode, they return true if the
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// immediate fits into a sign/zero extended 32-bit immediate (with the low bits
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// clear).
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def imm16ShiftedZExt : PatLeaf<(imm), [{
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// imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
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// immediate are set. Used by instructions like 'xoris'.
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return (N->getValue() & ~uint64_t(0xFFFF0000)) == 0;
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}], HI16>;
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def imm16ShiftedSExt : PatLeaf<(imm), [{
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// imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
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// immediate are set. Used by instructions like 'addis'. Identical to
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// imm16ShiftedZExt in 32-bit mode.
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if (N->getValue() & 0xFFFF) return false;
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if (N->getValueType(0) == MVT::i32)
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return true;
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@ -364,7 +376,7 @@ def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
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[]>;
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def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
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"addis $rD, $rA, $imm", IntGeneral,
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[(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
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[(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
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def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
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"la $rD, $sym($rA)", IntGeneral,
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[(set GPRC:$rD, (add GPRC:$rA,
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@ -380,7 +392,7 @@ def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm),
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[(set GPRC:$rD, immSExt16:$imm)]>;
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def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
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"lis $rD, $imm", IntGeneral,
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[(set GPRC:$rD, imm16Shifted:$imm)]>;
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[(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
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}
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let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
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def STB : DForm_3<38, (ops GPRC:$rS, memri:$src),
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@ -403,20 +415,20 @@ def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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isDOT;
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def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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"andis. $dst, $src1, $src2", IntGeneral,
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[(set GPRC:$dst, (and GPRC:$src1, imm16Shifted:$src2))]>,
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[(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
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isDOT;
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def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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"ori $dst, $src1, $src2", IntGeneral,
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[(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
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def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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"oris $dst, $src1, $src2", IntGeneral,
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[(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>;
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[(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
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def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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"xori $dst, $src1, $src2", IntGeneral,
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[(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
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def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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"xoris $dst, $src1, $src2", IntGeneral,
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[(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>;
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[(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
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def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral,
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[]>;
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def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
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