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Make class TargetMachine the common interface to all target-dependent

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information, including instr, sched, and reg information.
Rename files to match the primary classes they provide.
Commented out call to register allocation until more tests run correctly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@616 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vikram S. Adve 2001-09-18 13:01:29 +00:00
parent 0799fc479a
commit 0fb498017a
1 changed files with 64 additions and 49 deletions
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95
lib/Target/SparcV9/SparcV9TargetMachine.cpp
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@ -1,3 +1,4 @@
// $Id$
//*************************************************************************** //***************************************************************************
// File: // File:
// Sparc.cpp // Sparc.cpp
@ -18,12 +19,48 @@
#include "llvm/CodeGen/PhyRegAlloc.h" #include "llvm/CodeGen/PhyRegAlloc.h"
//***************************** Internal Functions *************************/
//----------------------------------------------------------------------------
// allocateSparcTargetMachine - Allocate and return a subclass of TargetMachine // allocateSparcTargetMachine - Allocate and return a subclass of TargetMachine
// that implements the Sparc backend. (the llvm/CodeGen/Sparc.h interface) // that implements the Sparc backend. (the llvm/CodeGen/Sparc.h interface)
//----------------------------------------------------------------------------
// //
TargetMachine *allocateSparcTargetMachine() { return new UltraSparc(); } TargetMachine *allocateSparcTargetMachine() { return new UltraSparc(); }
//----------------------------------------------------------------------------
// Entry point for register allocation for a module
//----------------------------------------------------------------------------
bool
AllocateRegisters(Method *M, TargetMachine &TM)
{
if ( (M)->isExternal() ) // don't process prototypes
return false;
if( DEBUG_RA ) {
cout << endl << "******************** Method "<< (M)->getName();
cout << " ********************" <<endl;
}
MethodLiveVarInfo LVI(M ); // Analyze live varaibles
LVI.analyze();
PhyRegAlloc PRA(M, TM , &LVI); // allocate registers
PRA.allocateRegisters();
if( DEBUG_RA ) cout << endl << "Register allocation complete!" << endl;
return false;
}
//***************************** External Classes **************************/
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
// class UltraSparcInstrInfo // class UltraSparcInstrInfo
// //
@ -396,63 +433,41 @@ void UltraSparcRegInfo::setCallArgColor(LiveRange *const LR,
// //
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
UltraSparc::UltraSparc() : TargetMachine("UltraSparc-Native"), UltraSparc::UltraSparc()
InstSchedulingInfo(&InstInfo), : TargetMachine("UltraSparc-Native"),
RegInfo( this ) { instrInfo(),
schedInfo(&instrInfo),
regInfo( this )
{
optSizeForSubWordData = 4; optSizeForSubWordData = 4;
minMemOpWordSize = 8; minMemOpWordSize = 8;
maxAtomicMemOpWordSize = 8; maxAtomicMemOpWordSize = 8;
zeroRegNum = RegInfo.getZeroReg(); // %g0 always gives 0 on Sparc
} }
bool
//---------------------------------------------------------------------------- UltraSparc::compileMethod(Method *M)
// Entry point for register allocation for a module {
//---------------------------------------------------------------------------- if (SelectInstructionsForMethod(M, *this))
void AllocateRegisters(Method *M, TargetMachine &TM)
{ {
if ( (M)->isExternal() ) // don't process prototypes
return;
if( DEBUG_RA ) {
cout << endl << "******************** Method "<< (M)->getName();
cout << " ********************" <<endl;
}
MethodLiveVarInfo LVI(M ); // Analyze live varaibles
LVI.analyze();
PhyRegAlloc PRA(M, TM , &LVI); // allocate registers
PRA.allocateRegisters();
if( DEBUG_RA ) cout << endl << "Register allocation complete!" << endl;
}
bool UltraSparc::compileMethod(Method *M) {
if (SelectInstructionsForMethod(M, *this)) {
cerr << "Instruction selection failed for method " << M->getName() cerr << "Instruction selection failed for method " << M->getName()
<< "\n\n"; << "\n\n";
return true; return true;
} }
if (ScheduleInstructionsWithSSA(M, *this, InstSchedulingInfo)) { if (ScheduleInstructionsWithSSA(M, *this))
{
cerr << "Instruction scheduling before allocation failed for method " cerr << "Instruction scheduling before allocation failed for method "
<< M->getName() << "\n\n"; << M->getName() << "\n\n";
return true; return true;
} }
AllocateRegisters(M, *this); // allocate registers // if (AllocateRegisters(M, *this)) // allocate registers
// {
// cerr << "Register allocation failed for method "
// << M->getName() << "\n\n";
// return true;
// }
return false; return false;
} }