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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-15 07:34:33 +00:00
Simplify the logic in the simple spiller and capitalize some variables
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16609 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
5f7d2d45fd
commit
0fc27ccdd3
@ -139,37 +139,41 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction& MF,
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// current machine instr, so it should be small.
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std::vector<unsigned> LoadedRegs;
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for (MachineFunction::iterator mbbi = MF.begin(), E = MF.end();
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mbbi != E; ++mbbi) {
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DEBUG(std::cerr << mbbi->getBasicBlock()->getName() << ":\n");
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for (MachineBasicBlock::iterator mii = mbbi->begin(),
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mie = mbbi->end(); mii != mie; ++mii) {
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for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) {
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MachineOperand& mop = mii->getOperand(i);
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if (mop.isRegister() && mop.getReg() &&
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MRegisterInfo::isVirtualRegister(mop.getReg())) {
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unsigned virtReg = mop.getReg();
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unsigned physReg = VRM.getPhys(virtReg);
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if (mop.isUse() && VRM.hasStackSlot(mop.getReg()) &&
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std::find(LoadedRegs.begin(), LoadedRegs.end(),
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virtReg) == LoadedRegs.end()) {
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MRI.loadRegFromStackSlot(*mbbi, mii, physReg,
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VRM.getStackSlot(virtReg));
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LoadedRegs.push_back(virtReg);
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DEBUG(std::cerr << '\t';
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prior(mii)->print(std::cerr, &TM));
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++NumLoads;
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}
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for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
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MBBI != E; ++MBBI) {
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DEBUG(std::cerr << MBBI->getBasicBlock()->getName() << ":\n");
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MachineBasicBlock &MBB = *MBBI;
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for (MachineBasicBlock::iterator MII = MBB.begin(),
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E = MBB.end(); MII != E; ++MII) {
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MachineInstr &MI = *MII;
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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MachineOperand &MOP = MI.getOperand(i);
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if (MOP.isRegister() && MOP.getReg() &&
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MRegisterInfo::isVirtualRegister(MOP.getReg())){
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unsigned VirtReg = MOP.getReg();
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unsigned PhysReg = VRM.getPhys(VirtReg);
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if (VRM.hasStackSlot(VirtReg)) {
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int StackSlot = VRM.getStackSlot(VirtReg);
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if (mop.isDef() && VRM.hasStackSlot(mop.getReg())) {
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MRI.storeRegToStackSlot(*mbbi, next(mii), physReg,
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VRM.getStackSlot(virtReg));
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++NumStores;
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if (MOP.isUse() &&
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std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
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== LoadedRegs.end()) {
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MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot);
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LoadedRegs.push_back(VirtReg);
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++NumLoads;
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DEBUG(std::cerr << '\t'; prior(MII)->print(std::cerr, &TM));
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}
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if (MOP.isDef()) {
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MRI.storeRegToStackSlot(MBB, next(MII), PhysReg,
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VRM.getStackSlot(VirtReg));
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++NumStores;
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}
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}
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mii->SetMachineOperandReg(i, physReg);
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MI.SetMachineOperandReg(i, PhysReg);
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}
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}
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DEBUG(std::cerr << '\t'; mii->print(std::cerr, &TM));
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DEBUG(std::cerr << '\t'; MI.print(std::cerr, &TM));
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LoadedRegs.clear();
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}
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}
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@ -199,52 +203,52 @@ namespace {
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bool runOnMachineFunction(MachineFunction &MF, const VirtRegMap &VRM);
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private:
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void vacateJustPhysReg(MachineBasicBlock& mbb,
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MachineBasicBlock::iterator mii,
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unsigned physReg);
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void vacateJustPhysReg(MachineBasicBlock& MBB,
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MachineBasicBlock::iterator MII,
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unsigned PhysReg);
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void vacatePhysReg(MachineBasicBlock& mbb,
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MachineBasicBlock::iterator mii,
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unsigned physReg) {
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vacateJustPhysReg(mbb, mii, physReg);
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for (const unsigned* as = MRI->getAliasSet(physReg); *as; ++as)
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vacateJustPhysReg(mbb, mii, *as);
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void vacatePhysReg(MachineBasicBlock& MBB,
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MachineBasicBlock::iterator MII,
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unsigned PhysReg) {
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vacateJustPhysReg(MBB, MII, PhysReg);
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for (const unsigned* as = MRI->getAliasSet(PhysReg); *as; ++as)
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vacateJustPhysReg(MBB, MII, *as);
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}
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void handleUse(MachineBasicBlock& mbb,
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MachineBasicBlock::iterator mii,
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unsigned virtReg,
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unsigned physReg) {
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void handleUse(MachineBasicBlock& MBB,
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MachineBasicBlock::iterator MII,
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unsigned VirtReg,
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unsigned PhysReg) {
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// check if we are replacing a previous mapping
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if (p2vMap_[physReg] != virtReg) {
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vacatePhysReg(mbb, mii, physReg);
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p2vMap_[physReg] = virtReg;
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if (p2vMap_[PhysReg] != VirtReg) {
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vacatePhysReg(MBB, MII, PhysReg);
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p2vMap_[PhysReg] = VirtReg;
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// load if necessary
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if (VRM->hasStackSlot(virtReg)) {
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MRI->loadRegFromStackSlot(mbb, mii, physReg,
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VRM->getStackSlot(virtReg));
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if (VRM->hasStackSlot(VirtReg)) {
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MRI->loadRegFromStackSlot(MBB, MII, PhysReg,
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VRM->getStackSlot(VirtReg));
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++NumLoads;
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DEBUG(std::cerr << "added: ";
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prior(mii)->print(std::cerr, TM));
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lastDef_[virtReg] = mii;
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prior(MII)->print(std::cerr, TM));
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lastDef_[VirtReg] = MII;
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}
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}
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}
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void handleDef(MachineBasicBlock& mbb,
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MachineBasicBlock::iterator mii,
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unsigned virtReg,
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unsigned physReg) {
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void handleDef(MachineBasicBlock& MBB,
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MachineBasicBlock::iterator MII,
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unsigned VirtReg,
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unsigned PhysReg) {
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// check if we are replacing a previous mapping
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if (p2vMap_[physReg] != virtReg)
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vacatePhysReg(mbb, mii, physReg);
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if (p2vMap_[PhysReg] != VirtReg)
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vacatePhysReg(MBB, MII, PhysReg);
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p2vMap_[physReg] = virtReg;
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dirty_[physReg] = true;
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lastDef_[virtReg] = mii;
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p2vMap_[PhysReg] = VirtReg;
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dirty_[PhysReg] = true;
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lastDef_[VirtReg] = MII;
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}
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void eliminateVirtRegsInMbb(MachineBasicBlock& mbb);
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void eliminateVirtRegsInMBB(MachineBasicBlock& MBB);
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};
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}
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@ -262,11 +266,11 @@ bool LocalSpiller::runOnMachineFunction(MachineFunction &mf,
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DEBUG(std::cerr << "********** Function: "
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<< MF->getFunction()->getName() << '\n');
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for (MachineFunction::iterator mbbi = MF->begin(),
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mbbe = MF->end(); mbbi != mbbe; ++mbbi) {
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for (MachineFunction::iterator MBB = MF->begin(), E = MF->end();
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MBB != E; ++MBB) {
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lastDef_.grow(MF->getSSARegMap()->getLastVirtReg());
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DEBUG(std::cerr << mbbi->getBasicBlock()->getName() << ":\n");
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eliminateVirtRegsInMbb(*mbbi);
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DEBUG(std::cerr << MBB->getBasicBlock()->getName() << ":\n");
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eliminateVirtRegsInMBB(*MBB);
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// clear map, dirty flag and last ref
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p2vMap_.assign(p2vMap_.size(), 0);
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dirty_.assign(dirty_.size(), false);
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@ -275,31 +279,31 @@ bool LocalSpiller::runOnMachineFunction(MachineFunction &mf,
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return true;
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}
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void LocalSpiller::vacateJustPhysReg(MachineBasicBlock& mbb,
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MachineBasicBlock::iterator mii,
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unsigned physReg) {
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unsigned virtReg = p2vMap_[physReg];
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if (dirty_[physReg] && VRM->hasStackSlot(virtReg)) {
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assert(lastDef_[virtReg] && "virtual register is mapped "
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void LocalSpiller::vacateJustPhysReg(MachineBasicBlock& MBB,
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MachineBasicBlock::iterator MII,
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unsigned PhysReg) {
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unsigned VirtReg = p2vMap_[PhysReg];
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if (dirty_[PhysReg] && VRM->hasStackSlot(VirtReg)) {
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assert(lastDef_[VirtReg] && "virtual register is mapped "
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"to a register and but was not defined!");
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MachineBasicBlock::iterator lastDef = lastDef_[virtReg];
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MachineBasicBlock::iterator lastDef = lastDef_[VirtReg];
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MachineBasicBlock::iterator nextLastRef = next(lastDef);
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MRI->storeRegToStackSlot(*lastDef->getParent(),
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nextLastRef,
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physReg,
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VRM->getStackSlot(virtReg));
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PhysReg,
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VRM->getStackSlot(VirtReg));
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++NumStores;
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DEBUG(std::cerr << "added: ";
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prior(nextLastRef)->print(std::cerr, TM);
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std::cerr << "after: ";
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lastDef->print(std::cerr, TM));
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lastDef_[virtReg] = 0;
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lastDef_[VirtReg] = 0;
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}
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p2vMap_[physReg] = 0;
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dirty_[physReg] = false;
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p2vMap_[PhysReg] = 0;
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dirty_[PhysReg] = false;
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}
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void LocalSpiller::eliminateVirtRegsInMbb(MachineBasicBlock &MBB) {
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void LocalSpiller::eliminateVirtRegsInMBB(MachineBasicBlock &MBB) {
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for (MachineBasicBlock::iterator MI = MBB.begin(), E = MBB.end();
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MI != E; ++MI) {
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@ -317,14 +321,14 @@ void LocalSpiller::eliminateVirtRegsInMbb(MachineBasicBlock &MBB) {
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MachineOperand& op = MI->getOperand(i);
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if (op.isRegister() && op.getReg() && op.isUse() &&
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MRegisterInfo::isVirtualRegister(op.getReg())) {
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unsigned virtReg = op.getReg();
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unsigned physReg = VRM->getPhys(virtReg);
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handleUse(MBB, MI, virtReg, physReg);
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MI->SetMachineOperandReg(i, physReg);
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unsigned VirtReg = op.getReg();
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unsigned PhysReg = VRM->getPhys(VirtReg);
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handleUse(MBB, MI, VirtReg, PhysReg);
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MI->SetMachineOperandReg(i, PhysReg);
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// mark as dirty if this is def&use
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if (op.isDef()) {
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dirty_[physReg] = true;
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lastDef_[virtReg] = MI;
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dirty_[PhysReg] = true;
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lastDef_[VirtReg] = MI;
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}
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}
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}
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@ -350,9 +354,9 @@ void LocalSpiller::eliminateVirtRegsInMbb(MachineBasicBlock &MBB) {
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if (MRegisterInfo::isPhysicalRegister(op.getReg()))
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vacatePhysReg(MBB, MI, op.getReg());
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else {
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unsigned physReg = VRM->getPhys(op.getReg());
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handleDef(MBB, MI, op.getReg(), physReg);
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MI->SetMachineOperandReg(i, physReg);
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unsigned PhysReg = VRM->getPhys(op.getReg());
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handleDef(MBB, MI, op.getReg(), PhysReg);
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MI->SetMachineOperandReg(i, PhysReg);
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}
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}
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