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Add pattern for OR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70720 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -54,7 +54,6 @@ MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
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setShiftAmountType(MVT::i8);
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setShiftAmountType(MVT::i8);
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setOperationAction(ISD::SRA, MVT::i16, Custom);
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setOperationAction(ISD::SRA, MVT::i16, Custom);
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setOperationAction(ISD::RET, MVT::Other, Custom);
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setOperationAction(ISD::RET, MVT::Other, Custom);
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}
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}
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@ -50,7 +50,6 @@ namespace llvm {
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SDValue LowerRET(SDValue Op, SelectionDAG &DAG);
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SDValue LowerRET(SDValue Op, SelectionDAG &DAG);
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SDValue LowerCCCArguments(SDValue Op, SelectionDAG &DAG);
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SDValue LowerCCCArguments(SDValue Op, SelectionDAG &DAG);
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SDValue LowerShifts(SDValue Op, SelectionDAG &DAG);
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SDValue LowerShifts(SDValue Op, SelectionDAG &DAG);
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private:
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private:
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const MSP430Subtarget &Subtarget;
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const MSP430Subtarget &Subtarget;
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const MSP430TargetMachine &TM;
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const MSP430TargetMachine &TM;
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@ -152,4 +152,15 @@ def SAR16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
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[(set GR16:$dst, (MSP430rra GR16:$src)),
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[(set GR16:$dst, (MSP430rra GR16:$src)),
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(implicit SR)]>;
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(implicit SR)]>;
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} // Defs = [SR]
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} // Defs = [SR]
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let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
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def OR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"bis.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>;
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}
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def OR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"bis.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (or GR16:$src1, imm:$src2))]>;
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} // isTwoAddress = 1
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} // isTwoAddress = 1
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