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R600/SI: Fix definition for s_cselect_b32
These were directly using the old base instruction class, and specifying the wrong register classes for operands. The operands can be the other special inputs besides SGPRs. The op name was also being directly used for the asm string, so this was printed without any operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221921 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -340,6 +340,11 @@ class SOP2_32 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
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opName#" $dst, $src0, $src1", pattern
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>;
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class SOP2_SELECT_32 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
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op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
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opName#" $dst, $src0, $src1 [$scc]", pattern
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>;
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class SOP2_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
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op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
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opName#" $dst, $src0, $src1", pattern
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@ -214,9 +214,8 @@ def S_MAX_U32 : SOP2_32 <0x00000009, "s_max_u32",
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[(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))]
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>;
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def S_CSELECT_B32 : SOP2 <
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0x0000000a, (outs SReg_32:$dst),
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(ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "s_cselect_b32",
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def S_CSELECT_B32 : SOP2_SELECT_32 <
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0x0000000a, "s_cselect_b32",
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[]
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>;
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