6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-14 17:34:41 +00:00
Code Issues Projects Releases Wiki Activity

add an observation

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40772 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2007-08-03 00:17:42 +00:00
parent b0e71edb6b
commit 107f54a002
1 changed files with 27 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
lib/Target/X86/README.txt
View File

@ -1103,3 +1103,30 @@ These instructions should go away:
movaps %xmm1, 192(%esp)
movaps %xmm1, 224(%esp)
movaps %xmm1, 176(%esp)
//===---------------------------------------------------------------------===//
This is a "commutable two-address" register coallescing deficiency:
define <4 x float> @test1(<4 x float> %V) {
entry:
%tmp8 = shufflevector <4 x float> %V, <4 x float> undef, <4 x i32> < i32 3, i32 2, i32 1, i32 0 > ; <<4 x float>> [#uses=1]
%add = add <4 x float> %tmp8, %V ; <<4 x float>> [#uses=1]
ret <4 x float> %add
}
this codegens to:
_test1:
pshufd $27, %xmm0, %xmm1
addps %xmm0, %xmm1
movaps %xmm1, %xmm0
ret
instead of:
_test1:
pshufd $27, %xmm0, %xmm1
addps %xmm1, %xmm0
ret