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Fix the x86 test-shrink optimization so that it doesn't shrink comparisons
when one of the bits being tested would end up being the sign bit in the narrower type, and a signed comparison is being performed, since this would change the result of the signed comparison. This fixes PR5132. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83670 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
parent
83815aeb29
commit
11596ed43c
@ -1625,6 +1625,68 @@ SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) {
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}
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}
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/// HasNoSignedComparisonUses - Test whether the given X86ISD::CMP node has
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/// any uses which require the SF or OF bits to be accurate.
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static bool HasNoSignedComparisonUses(SDNode *N) {
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// Examine each user of the node.
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for (SDNode::use_iterator UI = N->use_begin(),
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UE = N->use_end(); UI != UE; ++UI) {
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// Only examine CopyToReg uses.
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if (UI->getOpcode() != ISD::CopyToReg)
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return false;
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// Only examine CopyToReg uses that copy to EFLAGS.
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if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() !=
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X86::EFLAGS)
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return false;
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// Examine each user of the CopyToReg use.
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for (SDNode::use_iterator FlagUI = UI->use_begin(),
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FlagUE = UI->use_end(); FlagUI != FlagUE; ++FlagUI) {
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// Only examine the Flag result.
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if (FlagUI.getUse().getResNo() != 1) continue;
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// Anything unusual: assume conservatively.
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if (!FlagUI->isMachineOpcode()) return false;
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// Examine the opcode of the user.
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switch (FlagUI->getMachineOpcode()) {
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// These comparisons don't treat the most significant bit specially.
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case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr:
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case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr:
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case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm:
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case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm:
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case X86::JA: case X86::JAE: case X86::JB: case X86::JBE:
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case X86::JE: case X86::JNE: case X86::JP: case X86::JNP:
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case X86::CMOVA16rr: case X86::CMOVA16rm:
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case X86::CMOVA32rr: case X86::CMOVA32rm:
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case X86::CMOVA64rr: case X86::CMOVA64rm:
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case X86::CMOVAE16rr: case X86::CMOVAE16rm:
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case X86::CMOVAE32rr: case X86::CMOVAE32rm:
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case X86::CMOVAE64rr: case X86::CMOVAE64rm:
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case X86::CMOVB16rr: case X86::CMOVB16rm:
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case X86::CMOVB32rr: case X86::CMOVB32rm:
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case X86::CMOVB64rr: case X86::CMOVB64rm:
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case X86::CMOVBE16rr: case X86::CMOVBE16rm:
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case X86::CMOVBE32rr: case X86::CMOVBE32rm:
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case X86::CMOVBE64rr: case X86::CMOVBE64rm:
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case X86::CMOVE16rr: case X86::CMOVE16rm:
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case X86::CMOVE32rr: case X86::CMOVE32rm:
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case X86::CMOVE64rr: case X86::CMOVE64rm:
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case X86::CMOVNE16rr: case X86::CMOVNE16rm:
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case X86::CMOVNE32rr: case X86::CMOVNE32rm:
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case X86::CMOVNE64rr: case X86::CMOVNE64rm:
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case X86::CMOVNP16rr: case X86::CMOVNP16rm:
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case X86::CMOVNP32rr: case X86::CMOVNP32rm:
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case X86::CMOVNP64rr: case X86::CMOVNP64rm:
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case X86::CMOVP16rr: case X86::CMOVP16rm:
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case X86::CMOVP32rr: case X86::CMOVP32rm:
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case X86::CMOVP64rr: case X86::CMOVP64rm:
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continue;
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// Anything else: assume conservatively.
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default: return false;
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}
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}
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}
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return true;
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}
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SDNode *X86DAGToDAGISel::Select(SDValue N) {
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SDNode *Node = N.getNode();
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EVT NVT = Node->getValueType(0);
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@ -1978,7 +2040,9 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
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if (!C) break;
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// For example, convert "testl %eax, $8" to "testb %al, $8"
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if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0) {
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if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 &&
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(!(C->getZExtValue() & 0x80) ||
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HasNoSignedComparisonUses(Node))) {
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SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8);
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SDValue Reg = N0.getNode()->getOperand(0);
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@ -2004,7 +2068,9 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
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}
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// For example, "testl %eax, $2048" to "testb %ah, $8".
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if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0) {
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if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 &&
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(!(C->getZExtValue() & 0x8000) ||
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HasNoSignedComparisonUses(Node))) {
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// Shift the immediate right by 8 bits.
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SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,
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MVT::i8);
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@ -2034,7 +2100,9 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
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// For example, "testl %eax, $32776" to "testw %ax, $32776".
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if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 &&
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N0.getValueType() != MVT::i16) {
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N0.getValueType() != MVT::i16 &&
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(!(C->getZExtValue() & 0x8000) ||
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HasNoSignedComparisonUses(Node))) {
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SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16);
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SDValue Reg = N0.getNode()->getOperand(0);
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@ -2048,7 +2116,9 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
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// For example, "testq %rax, $268468232" to "testl %eax, $268468232".
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if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 &&
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N0.getValueType() == MVT::i64) {
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N0.getValueType() == MVT::i64 &&
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(!(C->getZExtValue() & 0x80000000) ||
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HasNoSignedComparisonUses(Node))) {
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SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
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SDValue Reg = N0.getNode()->getOperand(0);
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23
test/CodeGen/X86/test-shrink-bug.ll
Normal file
23
test/CodeGen/X86/test-shrink-bug.ll
Normal file
@ -0,0 +1,23 @@
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; RUN: llc < %s | FileCheck %s
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; Codegen shouldn't reduce the comparison down to testb $-1, %al
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; because that changes the result of the signed test.
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; PR5132
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; CHECK: testw $255, %ax
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
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target triple = "i386-apple-darwin10.0"
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@g_14 = global i8 -6, align 1 ; <i8*> [#uses=1]
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declare i32 @func_16(i8 signext %p_19, i32 %p_20) nounwind
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define i32 @func_35(i64 %p_38) nounwind ssp {
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entry:
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%tmp = load i8* @g_14 ; <i8> [#uses=2]
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%conv = zext i8 %tmp to i32 ; <i32> [#uses=1]
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%cmp = icmp sle i32 1, %conv ; <i1> [#uses=1]
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%conv2 = zext i1 %cmp to i32 ; <i32> [#uses=1]
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%call = call i32 @func_16(i8 signext %tmp, i32 %conv2) ssp ; <i32> [#uses=1]
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ret i32 1
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}
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