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Tighten up ARM reglist validation a bit.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138258 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-08-22 18:50:36 +00:00
parent d36b3e3681
commit 11e03e7c2d
1 changed files with 6 additions and 11 deletions
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17
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@ -24,6 +24,7 @@
#include "llvm/Target/TargetRegistry.h"
#include "llvm/Support/SourceMgr.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/OwningPtr.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
@ -1661,17 +1662,11 @@ parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Parser.Lex(); // Eat right curly brace token.
// Verify the register list.
SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
RI = Registers.begin(), RE = Registers.end();
unsigned HighRegNum = getARMRegisterNumbering(RI->first);
bool EmittedWarning = false;
DenseMap<unsigned, bool> RegMap;
RegMap[HighRegNum] = true;
for (++RI; RI != RE; ++RI) {
const std::pair<unsigned, SMLoc> &RegInfo = *RI;
unsigned HighRegNum = 0;
BitVector RegMap(32);
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
const std::pair<unsigned, SMLoc> &RegInfo = Registers[i];
unsigned Reg = getARMRegisterNumbering(RegInfo.first);
if (RegMap[Reg]) {
@ -1683,7 +1678,7 @@ parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Warning(RegInfo.second,
"register not in ascending order in register list");
RegMap[Reg] = true;
RegMap.set(Reg);
HighRegNum = std::max(Reg, HighRegNum);
}