mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Remove unneeded selection functions from HexagonISelDAGToDAG
- SelectSelect, and - SelectTruncate git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232569 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek
parent
89064930a0
commit
11f53b7797
@ -85,8 +85,6 @@ public:
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SDNode *SelectIndexedStore(StoreSDNode *ST, SDLoc dl);
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SDNode *SelectStore(SDNode *N);
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SDNode *SelectSHL(SDNode *N);
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SDNode *SelectSelect(SDNode *N);
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SDNode *SelectTruncate(SDNode *N);
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SDNode *SelectMul(SDNode *N);
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SDNode *SelectZeroExtend(SDNode *N);
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SDNode *SelectIntrinsicWChain(SDNode *N);
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@ -634,187 +632,6 @@ SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) {
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return SelectCode(N);
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}
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SDNode *HexagonDAGToDAGISel::SelectSelect(SDNode *N) {
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SDLoc dl(N);
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SDValue N0 = N->getOperand(0);
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if (N0.getOpcode() == ISD::SETCC) {
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SDValue N00 = N0.getOperand(0);
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if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) {
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SDValue N000 = N00.getOperand(0);
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SDValue N001 = N00.getOperand(1);
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if (cast<VTSDNode>(N001)->getVT() == MVT::i16) {
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SDValue N01 = N0.getOperand(1);
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SDValue N02 = N0.getOperand(2);
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// Pattern: (select:i32 (setcc:i1 (sext_inreg:i32 IntRegs:i32:$src2,
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// i16:Other),IntRegs:i32:$src1, SETLT:Other),IntRegs:i32:$src1,
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// IntRegs:i32:$src2)
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// Emits: (MAXh_rr:i32 IntRegs:i32:$src1, IntRegs:i32:$src2)
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// Pattern complexity = 9 cost = 1 size = 0.
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if (cast<CondCodeSDNode>(N02)->get() == ISD::SETLT) {
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SDValue N1 = N->getOperand(1);
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if (N01 == N1) {
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SDValue N2 = N->getOperand(2);
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if (N000 == N2 &&
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N0.getNode()->getValueType(N0.getResNo()) == MVT::i1 &&
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N00.getNode()->getValueType(N00.getResNo()) == MVT::i32) {
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SDNode *SextNode = CurDAG->getMachineNode(Hexagon::A2_sxth, dl,
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MVT::i32, N000);
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SDNode *Result = CurDAG->getMachineNode(Hexagon::A2_max, dl,
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MVT::i32,
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SDValue(SextNode, 0),
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N1);
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ReplaceUses(N, Result);
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return Result;
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}
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}
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}
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// Pattern: (select:i32 (setcc:i1 (sext_inreg:i32 IntRegs:i32:$src2,
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// i16:Other), IntRegs:i32:$src1, SETGT:Other), IntRegs:i32:$src1,
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// IntRegs:i32:$src2)
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// Emits: (MINh_rr:i32 IntRegs:i32:$src1, IntRegs:i32:$src2)
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// Pattern complexity = 9 cost = 1 size = 0.
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if (cast<CondCodeSDNode>(N02)->get() == ISD::SETGT) {
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SDValue N1 = N->getOperand(1);
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if (N01 == N1) {
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SDValue N2 = N->getOperand(2);
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if (N000 == N2 &&
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N0.getNode()->getValueType(N0.getResNo()) == MVT::i1 &&
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N00.getNode()->getValueType(N00.getResNo()) == MVT::i32) {
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SDNode *SextNode = CurDAG->getMachineNode(Hexagon::A2_sxth, dl,
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MVT::i32, N000);
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SDNode *Result = CurDAG->getMachineNode(Hexagon::A2_min, dl,
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MVT::i32,
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SDValue(SextNode, 0),
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N1);
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ReplaceUses(N, Result);
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return Result;
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}
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}
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}
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}
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}
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}
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return SelectCode(N);
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}
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SDNode *HexagonDAGToDAGISel::SelectTruncate(SDNode *N) {
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SDLoc dl(N);
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SDValue Shift = N->getOperand(0);
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//
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// %conv.i = sext i32 %tmp1 to i64
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// %conv2.i = sext i32 %add to i64
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// %mul.i = mul nsw i64 %conv2.i, %conv.i
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// %shr5.i = lshr i64 %mul.i, 32
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// %conv3.i = trunc i64 %shr5.i to i32
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//
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// --- match with the following ---
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//
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// %conv3.i = mpy (%tmp1, %add)
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//
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// Trunc to i32.
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if (N->getValueType(0) == MVT::i32) {
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// Trunc from i64.
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if (Shift.getNode()->getValueType(0) == MVT::i64) {
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// Trunc child is logical shift right.
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if (Shift.getOpcode() != ISD::SRL) {
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return SelectCode(N);
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}
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SDValue ShiftOp0 = Shift.getOperand(0);
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SDValue ShiftOp1 = Shift.getOperand(1);
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// Shift by const 32
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if (ShiftOp1.getOpcode() != ISD::Constant) {
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return SelectCode(N);
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}
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int32_t ShiftConst =
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cast<ConstantSDNode>(ShiftOp1.getNode())->getSExtValue();
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if (ShiftConst != 32) {
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return SelectCode(N);
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}
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// Shifting a i64 signed multiply
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SDValue Mul = ShiftOp0;
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if (Mul.getOpcode() != ISD::MUL) {
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return SelectCode(N);
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}
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SDValue MulOp0 = Mul.getOperand(0);
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SDValue MulOp1 = Mul.getOperand(1);
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SDValue OP0;
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SDValue OP1;
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// Handle sign_extend and sextload
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if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) {
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SDValue Sext0 = MulOp0.getOperand(0);
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if (Sext0.getNode()->getValueType(0) != MVT::i32) {
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return SelectCode(N);
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}
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OP0 = Sext0;
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} else if (MulOp0.getOpcode() == ISD::LOAD) {
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LoadSDNode *LD = cast<LoadSDNode>(MulOp0.getNode());
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if (LD->getMemoryVT() != MVT::i32 ||
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LD->getExtensionType() != ISD::SEXTLOAD ||
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LD->getAddressingMode() != ISD::UNINDEXED) {
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return SelectCode(N);
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}
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SDValue Chain = LD->getChain();
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SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
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OP0 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
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MVT::Other,
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LD->getBasePtr(),
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TargetConst0, Chain), 0);
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} else {
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return SelectCode(N);
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}
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// Same goes for the second operand.
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if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) {
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SDValue Sext1 = MulOp1.getOperand(0);
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if (Sext1.getNode()->getValueType(0) != MVT::i32)
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return SelectCode(N);
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OP1 = Sext1;
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} else if (MulOp1.getOpcode() == ISD::LOAD) {
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LoadSDNode *LD = cast<LoadSDNode>(MulOp1.getNode());
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if (LD->getMemoryVT() != MVT::i32 ||
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LD->getExtensionType() != ISD::SEXTLOAD ||
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LD->getAddressingMode() != ISD::UNINDEXED) {
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return SelectCode(N);
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}
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SDValue Chain = LD->getChain();
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SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
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OP1 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
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MVT::Other,
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LD->getBasePtr(),
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TargetConst0, Chain), 0);
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} else {
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return SelectCode(N);
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}
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// Generate a mpy instruction.
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SDNode *Result = CurDAG->getMachineNode(Hexagon::M2_mpy_up, dl, MVT::i32,
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OP0, OP1);
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ReplaceUses(N, Result);
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return Result;
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}
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}
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return SelectCode(N);
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}
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SDNode *HexagonDAGToDAGISel::SelectSHL(SDNode *N) {
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SDLoc dl(N);
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if (N->getValueType(0) == MVT::i32) {
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@ -1083,12 +900,6 @@ SDNode *HexagonDAGToDAGISel::Select(SDNode *N) {
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case ISD::STORE:
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return SelectStore(N);
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case ISD::SELECT:
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return SelectSelect(N);
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case ISD::TRUNCATE:
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return SelectTruncate(N);
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case ISD::MUL:
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return SelectMul(N);
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