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Dwarf register 0 is r0, remove incorrect entries.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132276 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2011-05-29 03:17:01 +00:00
parent a6d7345ec9
commit 11fd5c0cd9
1 changed files with 2 additions and 2 deletions
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4
lib/Target/PowerPC/PPCRegisterInfo.td
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@ -261,7 +261,7 @@ def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<[109]>;
// Carry bit. In the architecture this is really bit 0 of the XER register
// (which really is SPR register 1); this is the only bit interesting to a
// compiler.
def CARRY: SPR<1, "ca">, DwarfRegNum<[0]>;
def CARRY: SPR<1, "ca">;
// FP rounding mode: bits 30 and 31 of the FP status and control register
// This is not allocated as a normal register; it appears only in
@ -271,7 +271,7 @@ def CARRY: SPR<1, "ca">, DwarfRegNum<[0]>;
// return and call instructions are described as Uses of RM, so instructions
// that do nothing but change RM will not get deleted.
// Also, in the architecture it is not really a SPR; 512 is arbitrary.
def RM: SPR<512, "**ROUNDING MODE**">, DwarfRegNum<[0]>;
def RM: SPR<512, "**ROUNDING MODE**">;
/// Register classes
// Allocate volatiles first