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Dwarf register 0 is r0, remove incorrect entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132276 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -261,7 +261,7 @@ def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<[109]>;
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// Carry bit. In the architecture this is really bit 0 of the XER register
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// (which really is SPR register 1); this is the only bit interesting to a
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// compiler.
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def CARRY: SPR<1, "ca">, DwarfRegNum<[0]>;
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def CARRY: SPR<1, "ca">;
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// FP rounding mode: bits 30 and 31 of the FP status and control register
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// This is not allocated as a normal register; it appears only in
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@ -271,7 +271,7 @@ def CARRY: SPR<1, "ca">, DwarfRegNum<[0]>;
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// return and call instructions are described as Uses of RM, so instructions
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// that do nothing but change RM will not get deleted.
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// Also, in the architecture it is not really a SPR; 512 is arbitrary.
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def RM: SPR<512, "**ROUNDING MODE**">, DwarfRegNum<[0]>;
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def RM: SPR<512, "**ROUNDING MODE**">;
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/// Register classes
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// Allocate volatiles first
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