mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-20 10:30:03 +00:00
Finish up node ordering in ExpandNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91949 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
parent
4b6677f1c6
commit
122d06de74
@ -142,7 +142,7 @@ private:
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SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
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void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
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DebugLoc dl);
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DebugLoc dl, unsigned Order);
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SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
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SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
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@ -1633,7 +1633,7 @@ void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
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void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
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SDValue &LHS, SDValue &RHS,
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SDValue &CC,
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DebugLoc dl) {
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DebugLoc dl, unsigned Order) {
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EVT OpVT = LHS.getValueType();
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ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
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switch (TLI.getCondCodeAction(CCCode, OpVT)) {
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@ -1666,6 +1666,13 @@ void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
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LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
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RHS = SDValue();
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CC = SDValue();
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if (DisableScheduling) {
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DAG.AssignOrdering(LHS.getNode(), Order);
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DAG.AssignOrdering(SetCC1.getNode(), Order);
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DAG.AssignOrdering(SetCC2.getNode(), Order);
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}
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break;
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}
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}
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@ -2402,12 +2409,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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Tmp1 = DAG.getLoad(VT, dl, Tmp4, VAList, NULL, 0);
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Results.push_back(Tmp1);
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Results.push_back(Results[0].getValue(1));
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if (DisableScheduling) {
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DAG.AssignOrdering(Tmp1.getNode(), Order);
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DAG.AssignOrdering(Results[0].getValue(1).getNode(), Order);
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}
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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}
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case ISD::VACOPY: {
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@ -2523,18 +2525,13 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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Node->getValueType(0));
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Results.push_back(Tmp1);
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Results.push_back(Results[0].getValue(1));
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if (DisableScheduling) {
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DAG.AssignOrdering(Tmp1.getNode(), Order);
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DAG.AssignOrdering(Results[0].getValue(1).getNode(), Order);
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}
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} else {
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Tmp1 = DAG.getUNDEF(Node->getValueType(0));
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Results.push_back(Tmp1);
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Results.push_back(Node->getOperand(0));
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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}
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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case ISD::STACKRESTORE:
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// Expand to CopyToReg if the target set StackPointerRegisterToSaveRestore.
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@ -2703,12 +2700,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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Node->getValueType(0));
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Results.push_back(Tmp1);
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Results.push_back(Results[0].getValue(1));
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if (DisableScheduling) {
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DAG.AssignOrdering(Tmp1.getNode(), Order);
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DAG.AssignOrdering(Results[0].getValue(1).getNode(), Order);
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}
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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}
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case ISD::EXCEPTIONADDR: {
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@ -2718,12 +2710,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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Node->getValueType(0));
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Results.push_back(Tmp1);
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Results.push_back(Results[0].getValue(1));
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if (DisableScheduling) {
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DAG.AssignOrdering(Tmp1.getNode(), Order);
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DAG.AssignOrdering(Results[0].getValue(1).getNode(), Order);
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}
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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}
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case ISD::SUB: {
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@ -2757,10 +2744,13 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
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Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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} else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
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// X % Y -> X-X/Y*Y
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Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
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} else if (isSigned) {
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Tmp1 = ExpandIntLibCall(Node, true,
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@ -2775,6 +2765,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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}
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Results.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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}
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case ISD::UDIV:
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@ -2797,6 +2788,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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RTLIB::UDIV_I16, RTLIB::UDIV_I32,
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RTLIB::UDIV_I64, RTLIB::UDIV_I128);
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Results.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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}
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case ISD::MULHU:
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@ -2810,6 +2802,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
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Node->getOperand(1));
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Results.push_back(Tmp1.getValue(1));
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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}
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case ISD::MUL: {
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@ -2825,6 +2818,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
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bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
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unsigned OpToUse = 0;
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if (HasSMUL_LOHI && !HasMULHS) {
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OpToUse = ISD::SMUL_LOHI;
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} else if (HasUMUL_LOHI && !HasMULHU) {
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@ -2834,16 +2828,21 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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} else if (HasUMUL_LOHI) {
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OpToUse = ISD::UMUL_LOHI;
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}
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if (OpToUse) {
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Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
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Node->getOperand(1)));
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Tmp1 = DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
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Node->getOperand(1));
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Results.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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}
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Tmp1 = ExpandIntLibCall(Node, false,
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RTLIB::MUL_I8,
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RTLIB::MUL_I16, RTLIB::MUL_I32,
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RTLIB::MUL_I64, RTLIB::MUL_I128);
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Results.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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}
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case ISD::SADDO:
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@ -2854,8 +2853,9 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
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LHS, RHS);
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Results.push_back(Sum);
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EVT OType = Node->getValueType(1);
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if (DisableScheduling) DAG.AssignOrdering(Sum.getNode(), Order);
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EVT OType = Node->getValueType(1);
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SDValue Zero = DAG.getConstant(0, LHS.getValueType());
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// LHSSign -> LHS >= 0
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@ -2878,6 +2878,16 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
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Results.push_back(Cmp);
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if (DisableScheduling) {
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DAG.AssignOrdering(LHSSign.getNode(), Order);
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DAG.AssignOrdering(RHSSign.getNode(), Order);
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DAG.AssignOrdering(SignsMatch.getNode(), Order);
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DAG.AssignOrdering(SumSign.getNode(), Order);
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DAG.AssignOrdering(SumSignNE.getNode(), Order);
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DAG.AssignOrdering(Cmp.getNode(), Order);
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}
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break;
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}
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case ISD::UADDO:
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@ -2888,9 +2898,17 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
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LHS, RHS);
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Results.push_back(Sum);
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Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
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Node->getOpcode () == ISD::UADDO ?
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ISD::SETULT : ISD::SETUGT));
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Tmp1 = DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
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Node->getOpcode () == ISD::UADDO ?
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ISD::SETULT : ISD::SETUGT);
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Results.push_back(Tmp1);
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if (DisableScheduling) {
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DAG.AssignOrdering(Sum.getNode(), Order);
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DAG.AssignOrdering(Tmp1.getNode(), Order);
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}
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break;
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}
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case ISD::UMULO:
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@ -2904,6 +2922,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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{ { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
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{ ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
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bool isSigned = Node->getOpcode() == ISD::SMULO;
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if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
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BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
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TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
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@ -2920,6 +2939,12 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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DAG.getIntPtrConstant(0));
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TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
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DAG.getIntPtrConstant(1));
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if (DisableScheduling) {
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DAG.AssignOrdering(LHS.getNode(), Order);
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DAG.AssignOrdering(RHS.getNode(), Order);
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DAG.AssignOrdering(Tmp1.getNode(), Order);
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}
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} else {
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// FIXME: We should be able to fall back to a libcall with an illegal
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// type in some cases cases.
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@ -2927,6 +2952,12 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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// performance hit in the general case.
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llvm_unreachable("Don't know how to expand this operation yet!");
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}
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if (DisableScheduling) {
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DAG.AssignOrdering(BottomHalf.getNode(), Order);
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DAG.AssignOrdering(TopHalf.getNode(), Order);
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}
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if (isSigned) {
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Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy());
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Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
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@ -2936,34 +2967,52 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
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DAG.getConstant(0, VT), ISD::SETNE);
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}
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Results.push_back(BottomHalf);
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Results.push_back(TopHalf);
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if (DisableScheduling) {
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DAG.AssignOrdering(BottomHalf.getNode(), Order);
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DAG.AssignOrdering(TopHalf.getNode(), Order);
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}
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break;
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}
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case ISD::BUILD_PAIR: {
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EVT PairTy = Node->getValueType(0);
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Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
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Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
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Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
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Tmp3 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
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DAG.getConstant(PairTy.getSizeInBits()/2,
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TLI.getShiftAmountTy()));
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Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
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Tmp4 = DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp3);
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Results.push_back(Tmp4);
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if (DisableScheduling) {
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DAG.AssignOrdering(Tmp1.getNode(), Order);
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DAG.AssignOrdering(Tmp2.getNode(), Order);
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DAG.AssignOrdering(Tmp3.getNode(), Order);
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DAG.AssignOrdering(Tmp4.getNode(), Order);
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}
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break;
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}
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case ISD::SELECT:
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Tmp1 = Node->getOperand(0);
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Tmp2 = Node->getOperand(1);
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Tmp3 = Node->getOperand(2);
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if (Tmp1.getOpcode() == ISD::SETCC) {
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if (Tmp1.getOpcode() == ISD::SETCC)
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Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
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Tmp2, Tmp3,
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cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
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} else {
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else
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Tmp1 = DAG.getSelectCC(dl, Tmp1,
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DAG.getConstant(0, Tmp1.getValueType()),
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Tmp2, Tmp3, ISD::SETNE);
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}
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Results.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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case ISD::BR_JT: {
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SDValue Chain = Node->getOperand(0);
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@ -2973,9 +3022,11 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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EVT PTy = TLI.getPointerTy();
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MachineFunction &MF = DAG.getMachineFunction();
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unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
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Index= DAG.getNode(ISD::MUL, dl, PTy,
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Index = DAG.getNode(ISD::MUL, dl, PTy,
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Index, DAG.getConstant(EntrySize, PTy));
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SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
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if (DisableScheduling) DAG.AssignOrdering(Addr.getNode(), Order);
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EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
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SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
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@ -2983,13 +3034,24 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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Addr = LD;
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if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
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// For PIC, the sequence is:
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// BRIND(load(Jumptable + index) + RelocBase)
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//
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// BRIND(load(Jumptable + index) + RelocBase)
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//
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// RelocBase can be JumpTable, GOT or some sort of global base.
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Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
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TLI.getPICJumpTableRelocBase(Table, DAG));
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if (DisableScheduling) DAG.AssignOrdering(Addr.getNode(), Order);
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}
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Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
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Results.push_back(Tmp1);
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if (DisableScheduling) {
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DAG.AssignOrdering(Tmp1.getNode(), Order);
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DAG.AssignOrdering(Index.getNode(), Order);
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DAG.AssignOrdering(LD.getNode(), Order);
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}
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break;
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}
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case ISD::BRCOND:
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@ -2997,24 +3059,26 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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// Node.
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Tmp1 = Node->getOperand(0);
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Tmp2 = Node->getOperand(1);
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if (Tmp2.getOpcode() == ISD::SETCC) {
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if (Tmp2.getOpcode() == ISD::SETCC)
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Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
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Tmp1, Tmp2.getOperand(2),
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Tmp2.getOperand(0), Tmp2.getOperand(1),
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Node->getOperand(2));
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} else {
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else
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Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
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DAG.getCondCode(ISD::SETNE), Tmp2,
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DAG.getConstant(0, Tmp2.getValueType()),
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Node->getOperand(2));
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}
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Results.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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case ISD::SETCC: {
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Tmp1 = Node->getOperand(0);
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Tmp2 = Node->getOperand(1);
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Tmp3 = Node->getOperand(2);
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LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
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LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl, Order);
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// If we expanded the SETCC into an AND/OR, return the new node
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if (Tmp2.getNode() == 0) {
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@ -3028,6 +3092,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
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DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
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Results.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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}
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case ISD::SELECT_CC: {
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@ -3038,7 +3103,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
|
||||
SDValue CC = Node->getOperand(4);
|
||||
|
||||
LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
|
||||
Tmp1, Tmp2, CC, dl);
|
||||
Tmp1, Tmp2, CC, dl, Order);
|
||||
|
||||
assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
|
||||
Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
|
||||
@ -3046,6 +3111,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
|
||||
Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
|
||||
Tmp3, Tmp4, CC);
|
||||
Results.push_back(Tmp1);
|
||||
if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
|
||||
break;
|
||||
}
|
||||
case ISD::BR_CC: {
|
||||
@ -3055,7 +3121,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
|
||||
Tmp4 = Node->getOperand(1); // CC
|
||||
|
||||
LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
|
||||
Tmp2, Tmp3, Tmp4, dl);
|
||||
Tmp2, Tmp3, Tmp4, dl, Order);
|
||||
LastCALLSEQ_END = DAG.getEntryNode();
|
||||
|
||||
assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
|
||||
@ -3064,6 +3130,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
|
||||
Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
|
||||
Tmp3, Node->getOperand(4));
|
||||
Results.push_back(Tmp1);
|
||||
if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
|
||||
break;
|
||||
}
|
||||
case ISD::GLOBAL_OFFSET_TABLE:
|
||||
@ -3081,6 +3148,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void SelectionDAGLegalize::PromoteNode(SDNode *Node,
|
||||
SmallVectorImpl<SDValue> &Results) {
|
||||
EVT OVT = Node->getValueType(0);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user