mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Teach the x86 backend to eliminate "test" instructions by using the EFLAGS
result from add, sub, inc, and dec instructions in simple cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66004 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
parent
0744f09efc
commit
12bbc52aa7
@ -5361,6 +5361,87 @@ SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
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return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
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}
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/// Emit nodes that will be selected as "test Op0,Op0", or something
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/// equivalent.
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SDValue X86TargetLowering::EmitTest(SDValue Op, SelectionDAG &DAG) {
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DebugLoc dl = Op.getDebugLoc();
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if (Op.getResNo() == 0) {
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unsigned Opcode = 0;
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switch (Op.getNode()->getOpcode()) {
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case ISD::ADD:
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// Due to an isel shortcoming, be conservative if this add is likely to
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// be selected as part of a load-modify-store instruction. When the root
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// node in a match is a store, isel doesn't know how to remap non-chain
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// non-flag uses of other nodes in the match, such as the ADD in this
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// case. This leads to the ADD being left around and reselected, with
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// the result being two adds in the output.
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for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
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UE = Op.getNode()->use_end(); UI != UE; ++UI)
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if (UI->getOpcode() == ISD::STORE)
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goto default_case;
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// An add of one will be selected as an INC.
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if (ConstantSDNode *C =
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dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1)))
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if (C->getAPIntValue() == 1) {
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Opcode = X86ISD::INC;
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break;
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}
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// Otherwise use a regular EFLAGS-setting add.
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Opcode = X86ISD::ADD;
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break;
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case ISD::SUB:
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// Due to the ISEL shortcoming noted above, be conservative if this sub is
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// likely to be selected as part of a load-modify-store instruction.
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for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
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UE = Op.getNode()->use_end(); UI != UE; ++UI)
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if (UI->getOpcode() == ISD::STORE)
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goto default_case;
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// A subtract of one will be selected as a DEC.
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if (ConstantSDNode *C =
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dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1)))
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if (C->getAPIntValue() == 1) {
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Opcode = X86ISD::DEC;
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break;
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}
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// Otherwise use a regular EFLAGS-setting sub.
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Opcode = X86ISD::SUB;
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break;
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case X86ISD::ADD:
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case X86ISD::SUB:
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case X86ISD::INC:
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case X86ISD::DEC:
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return SDValue(Op.getNode(), 1);
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default:
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default_case:
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break;
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}
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if (Opcode != 0) {
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const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(), MVT::i32);
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SmallVector<SDValue, 4> Ops;
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for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i)
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Ops.push_back(Op.getOperand(i));
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SDValue New = DAG.getNode(Opcode, dl, VTs, 2, &Ops[0], Ops.size());
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DAG.ReplaceAllUsesWith(Op, New);
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return SDValue(New.getNode(), 1);
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}
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}
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return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
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DAG.getConstant(0, Op.getValueType()));
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}
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/// Emit nodes that will be selected as "cmp Op0,Op1", or something
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/// equivalent.
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SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, SelectionDAG &DAG) {
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
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if (C->getAPIntValue() == 0)
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return EmitTest(Op0, DAG);
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DebugLoc dl = Op0.getDebugLoc();
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return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
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}
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SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
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assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
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SDValue Op0 = Op.getOperand(0);
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@ -5423,7 +5504,7 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
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bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
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unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
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SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
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SDValue Cond = EmitCmp(Op0, Op1, DAG);
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return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
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DAG.getConstant(X86CC, MVT::i8), Cond);
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}
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@ -5542,8 +5623,20 @@ SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
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}
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// isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
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static bool isX86LogicalCmp(unsigned Opc) {
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return Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI;
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static bool isX86LogicalCmp(SDValue Op) {
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unsigned Opc = Op.getNode()->getOpcode();
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if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
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return true;
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if (Op.getResNo() == 1 &&
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Opc == X86ISD::ADD ||
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Opc == X86ISD::SUB ||
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Opc == X86ISD::SMUL ||
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Opc == X86ISD::UMUL ||
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Opc == X86ISD::INC ||
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Opc == X86ISD::DEC)
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return true;
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return false;
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}
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SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
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@ -5569,7 +5662,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
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!isScalarFPTypeInSSEReg(VT)) // FPStack?
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IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
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if ((isX86LogicalCmp(Opc) && !IllegalFPCMov) || Opc == X86ISD::BT) { // FIXME
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if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || Opc == X86ISD::BT) { // FIXME
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Cond = Cmp;
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addTest = false;
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}
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@ -5577,8 +5670,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
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if (addTest) {
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CC = DAG.getConstant(X86::COND_NE, MVT::i8);
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Cond= DAG.getNode(X86ISD::CMP, dl, MVT::i32, Cond,
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DAG.getConstant(0, MVT::i8));
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Cond = EmitTest(Cond, DAG);
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}
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const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(),
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@ -5646,7 +5738,7 @@ SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
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SDValue Cmp = Cond.getOperand(1);
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unsigned Opc = Cmp.getOpcode();
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// FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
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if (isX86LogicalCmp(Opc) || Opc == X86ISD::BT) {
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if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
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Cond = Cmp;
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addTest = false;
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} else {
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@ -5665,13 +5757,12 @@ SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
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unsigned CondOpc;
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if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
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SDValue Cmp = Cond.getOperand(0).getOperand(1);
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unsigned Opc = Cmp.getOpcode();
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if (CondOpc == ISD::OR) {
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// Also, recognize the pattern generated by an FCMP_UNE. We can emit
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// two branches instead of an explicit OR instruction with a
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// separate test.
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if (Cmp == Cond.getOperand(1).getOperand(1) &&
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isX86LogicalCmp(Opc)) {
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isX86LogicalCmp(Cmp)) {
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CC = Cond.getOperand(0).getOperand(0);
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Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
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Chain, Dest, CC, Cmp);
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@ -5686,7 +5777,7 @@ SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
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// have a fall-through edge, because this requires an explicit
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// jmp when the condition is false.
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if (Cmp == Cond.getOperand(1).getOperand(1) &&
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isX86LogicalCmp(Opc) &&
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isX86LogicalCmp(Cmp) &&
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Op.getNode()->hasOneUse()) {
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X86::CondCode CCode =
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(X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
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@ -5729,8 +5820,7 @@ SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
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if (addTest) {
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CC = DAG.getConstant(X86::COND_NE, MVT::i8);
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Cond= DAG.getNode(X86ISD::CMP, dl, MVT::i32, Cond,
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DAG.getConstant(0, MVT::i8));
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Cond = EmitTest(Cond, DAG);
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}
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return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
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Chain, Dest, CC, Cond);
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@ -6663,6 +6753,14 @@ SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
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switch (Op.getOpcode()) {
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default: assert(0 && "Unknown ovf instruction!");
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case ISD::SADDO:
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// A subtract of one will be selected as a INC. Note that INC doesn't
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// set CF, so we can't do this for UADDO.
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
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if (C->getAPIntValue() == 1) {
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BaseOp = X86ISD::INC;
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Cond = X86::COND_O;
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break;
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}
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BaseOp = X86ISD::ADD;
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Cond = X86::COND_O;
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break;
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@ -6671,6 +6769,14 @@ SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
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Cond = X86::COND_B;
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break;
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case ISD::SSUBO:
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// A subtract of one will be selected as a DEC. Note that DEC doesn't
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// set CF, so we can't do this for USUBO.
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
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if (C->getAPIntValue() == 1) {
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BaseOp = X86ISD::DEC;
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Cond = X86::COND_O;
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break;
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}
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BaseOp = X86ISD::SUB;
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Cond = X86::COND_O;
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break;
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@ -7011,6 +7117,8 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::SUB: return "X86ISD::SUB";
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case X86ISD::SMUL: return "X86ISD::SMUL";
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case X86ISD::UMUL: return "X86ISD::UMUL";
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case X86ISD::INC: return "X86ISD::INC";
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case X86ISD::DEC: return "X86ISD::DEC";
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}
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}
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@ -7809,6 +7917,8 @@ void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
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case X86ISD::SUB:
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case X86ISD::SMUL:
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case X86ISD::UMUL:
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case X86ISD::INC:
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case X86ISD::DEC:
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// These nodes' second result is a boolean.
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if (Op.getResNo() == 0)
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break;
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@ -235,9 +235,9 @@ namespace llvm {
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PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ,
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PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ,
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// ADD, SUB, SMUL, UMUL - Arithmetic operations with overflow/carry
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// intrinsics.
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ADD, SUB, SMUL, UMUL
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// ADD, SUB, SMUL, UMUL, etc. - Arithmetic operations with FLAGS results.
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ADD, SUB, SMUL, UMUL,
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INC, DEC
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};
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}
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@ -659,6 +659,14 @@ namespace llvm {
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MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr,
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MachineBasicBlock *BB,
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unsigned cmovOpc) const;
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/// Emit nodes that will be selected as "test Op0,Op0", or something
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/// equivalent.
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SDValue EmitTest(SDValue Op0, SelectionDAG &DAG);
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/// Emit nodes that will be selected as "cmp Op0,Op1", or something
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/// equivalent.
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SDValue EmitCmp(SDValue Op0, SDValue Op1, SelectionDAG &DAG);
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};
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namespace X86 {
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@ -1632,101 +1632,113 @@ def : Pat<(subc GR64:$src1, imm:$src2),
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(SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
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//===----------------------------------------------------------------------===//
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// Overflow Patterns
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// EFLAGS-defining Patterns
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//===----------------------------------------------------------------------===//
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// Register-Register Addition with Overflow
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def : Pat<(parallel (X86add_ovf GR64:$src1, GR64:$src2),
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// Register-Register Addition with EFLAGS result
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def : Pat<(parallel (X86add_flag GR64:$src1, GR64:$src2),
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(implicit EFLAGS)),
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(ADD64rr GR64:$src1, GR64:$src2)>;
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// Register-Integer Addition with Overflow
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def : Pat<(parallel (X86add_ovf GR64:$src1, i64immSExt8:$src2),
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// Register-Integer Addition with EFLAGS result
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def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt8:$src2),
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(implicit EFLAGS)),
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(ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
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def : Pat<(parallel (X86add_ovf GR64:$src1, i64immSExt32:$src2),
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def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt32:$src2),
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(implicit EFLAGS)),
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(ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
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// Register-Memory Addition with Overflow
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def : Pat<(parallel (X86add_ovf GR64:$src1, (load addr:$src2)),
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// Register-Memory Addition with EFLAGS result
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def : Pat<(parallel (X86add_flag GR64:$src1, (loadi64 addr:$src2)),
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(implicit EFLAGS)),
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(ADD64rm GR64:$src1, addr:$src2)>;
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// Memory-Register Addition with Overflow
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def : Pat<(parallel (store (X86add_ovf (load addr:$dst), GR64:$src2),
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// Memory-Register Addition with EFLAGS result
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def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), GR64:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(ADD64mr addr:$dst, GR64:$src2)>;
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def : Pat<(parallel (store (X86add_ovf (load addr:$dst), i64immSExt8:$src2),
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def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt8:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(ADD64mi8 addr:$dst, i64immSExt8:$src2)>;
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def : Pat<(parallel (store (X86add_ovf (load addr:$dst), i64immSExt32:$src2),
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def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt32:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(ADD64mi32 addr:$dst, i64immSExt32:$src2)>;
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// Register-Register Subtraction with Overflow
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def : Pat<(parallel (X86sub_ovf GR64:$src1, GR64:$src2),
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// Register-Register Subtraction with EFLAGS result
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def : Pat<(parallel (X86sub_flag GR64:$src1, GR64:$src2),
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(implicit EFLAGS)),
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(SUB64rr GR64:$src1, GR64:$src2)>;
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// Register-Memory Subtraction with Overflow
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def : Pat<(parallel (X86sub_ovf GR64:$src1, (load addr:$src2)),
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// Register-Memory Subtraction with EFLAGS result
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def : Pat<(parallel (X86sub_flag GR64:$src1, (loadi64 addr:$src2)),
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(implicit EFLAGS)),
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(SUB64rm GR64:$src1, addr:$src2)>;
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// Register-Integer Subtraction with Overflow
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def : Pat<(parallel (X86sub_ovf GR64:$src1, i64immSExt8:$src2),
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// Register-Integer Subtraction with EFLAGS result
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def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt8:$src2),
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(implicit EFLAGS)),
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(SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
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def : Pat<(parallel (X86sub_ovf GR64:$src1, i64immSExt32:$src2),
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def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt32:$src2),
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(implicit EFLAGS)),
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(SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
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// Memory-Register Subtraction with Overflow
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def : Pat<(parallel (store (X86sub_ovf (load addr:$dst), GR64:$src2),
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// Memory-Register Subtraction with EFLAGS result
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def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), GR64:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(SUB64mr addr:$dst, GR64:$src2)>;
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// Memory-Integer Subtraction with Overflow
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def : Pat<(parallel (store (X86sub_ovf (load addr:$dst), i64immSExt8:$src2),
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// Memory-Integer Subtraction with EFLAGS result
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def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt8:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(SUB64mi8 addr:$dst, i64immSExt8:$src2)>;
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def : Pat<(parallel (store (X86sub_ovf (load addr:$dst), i64immSExt32:$src2),
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def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt32:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(SUB64mi32 addr:$dst, i64immSExt32:$src2)>;
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// Register-Register Signed Integer Multiplication with Overflow
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def : Pat<(parallel (X86smul_ovf GR64:$src1, GR64:$src2),
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// Register-Register Signed Integer Multiplication with EFLAGS result
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def : Pat<(parallel (X86smul_flag GR64:$src1, GR64:$src2),
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(implicit EFLAGS)),
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(IMUL64rr GR64:$src1, GR64:$src2)>;
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// Register-Memory Signed Integer Multiplication with Overflow
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||||
def : Pat<(parallel (X86smul_ovf GR64:$src1, (load addr:$src2)),
|
||||
// Register-Memory Signed Integer Multiplication with EFLAGS result
|
||||
def : Pat<(parallel (X86smul_flag GR64:$src1, (loadi64 addr:$src2)),
|
||||
(implicit EFLAGS)),
|
||||
(IMUL64rm GR64:$src1, addr:$src2)>;
|
||||
|
||||
// Register-Integer Signed Integer Multiplication with Overflow
|
||||
def : Pat<(parallel (X86smul_ovf GR64:$src1, i64immSExt8:$src2),
|
||||
// Register-Integer Signed Integer Multiplication with EFLAGS result
|
||||
def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt8:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
|
||||
def : Pat<(parallel (X86smul_ovf GR64:$src1, i64immSExt32:$src2),
|
||||
def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt32:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
|
||||
|
||||
// Memory-Integer Signed Integer Multiplication with Overflow
|
||||
def : Pat<(parallel (X86smul_ovf (load addr:$src1), i64immSExt8:$src2),
|
||||
// Memory-Integer Signed Integer Multiplication with EFLAGS result
|
||||
def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt8:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
|
||||
def : Pat<(parallel (X86smul_ovf (load addr:$src1), i64immSExt32:$src2),
|
||||
def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt32:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
|
||||
|
||||
// INC and DEC with EFLAGS result. Note that these do not set CF.
|
||||
def : Pat<(parallel (X86inc_flag GR64:$src), (implicit EFLAGS)),
|
||||
(INC64r GR64:$src)>;
|
||||
def : Pat<(parallel (store (i64 (X86inc_flag (loadi64 addr:$dst))), addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(INC64m addr:$dst)>;
|
||||
def : Pat<(parallel (X86dec_flag GR64:$src), (implicit EFLAGS)),
|
||||
(DEC64r GR64:$src)>;
|
||||
def : Pat<(parallel (store (i64 (X86dec_flag (loadi64 addr:$dst))), addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(DEC64m addr:$dst)>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// X86-64 SSE Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
@ -27,11 +27,13 @@ def SDTX86Cmov : SDTypeProfile<1, 4,
|
||||
[SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
|
||||
SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
|
||||
|
||||
def SDTUnaryArithOvf : SDTypeProfile<1, 1,
|
||||
[SDTCisInt<0>]>;
|
||||
def SDTBinaryArithOvf : SDTypeProfile<1, 2,
|
||||
[SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
|
||||
SDTCisInt<0>]>;
|
||||
// Unary and binary operator instructions that set EFLAGS as a side-effect.
|
||||
def SDTUnaryArithWithFlags : SDTypeProfile<1, 1,
|
||||
[SDTCisInt<0>]>;
|
||||
def SDTBinaryArithWithFlags : SDTypeProfile<1, 2,
|
||||
[SDTCisSameAs<0, 1>,
|
||||
SDTCisSameAs<0, 2>,
|
||||
SDTCisInt<0>]>;
|
||||
|
||||
def SDTX86BrCond : SDTypeProfile<0, 3,
|
||||
[SDTCisVT<0, OtherVT>,
|
||||
@ -148,10 +150,12 @@ def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
|
||||
def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
|
||||
[SDNPHasChain, SDNPOptInFlag]>;
|
||||
|
||||
def X86add_ovf : SDNode<"X86ISD::ADD", SDTBinaryArithOvf>;
|
||||
def X86sub_ovf : SDNode<"X86ISD::SUB", SDTBinaryArithOvf>;
|
||||
def X86smul_ovf : SDNode<"X86ISD::SMUL", SDTBinaryArithOvf>;
|
||||
def X86umul_ovf : SDNode<"X86ISD::UMUL", SDTUnaryArithOvf>;
|
||||
def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags>;
|
||||
def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
|
||||
def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags>;
|
||||
def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags>;
|
||||
def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
|
||||
def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// X86 Operand Definitions.
|
||||
@ -3486,217 +3490,251 @@ def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
|
||||
(SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Overflow Patterns
|
||||
// EFLAGS-defining Patterns
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Register-Register Addition with Overflow
|
||||
def : Pat<(parallel (X86add_ovf GR8:$src1, GR8:$src2),
|
||||
// Register-Register Addition with EFLAGS result
|
||||
def : Pat<(parallel (X86add_flag GR8:$src1, GR8:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(ADD8rr GR8:$src1, GR8:$src2)>;
|
||||
|
||||
// Register-Register Addition with Overflow
|
||||
def : Pat<(parallel (X86add_ovf GR16:$src1, GR16:$src2),
|
||||
// Register-Register Addition with EFLAGS result
|
||||
def : Pat<(parallel (X86add_flag GR16:$src1, GR16:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(ADD16rr GR16:$src1, GR16:$src2)>;
|
||||
def : Pat<(parallel (X86add_ovf GR32:$src1, GR32:$src2),
|
||||
def : Pat<(parallel (X86add_flag GR32:$src1, GR32:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(ADD32rr GR32:$src1, GR32:$src2)>;
|
||||
|
||||
// Register-Memory Addition with Overflow
|
||||
def : Pat<(parallel (X86add_ovf GR8:$src1, (load addr:$src2)),
|
||||
// Register-Memory Addition with EFLAGS result
|
||||
def : Pat<(parallel (X86add_flag GR8:$src1, (loadi8 addr:$src2)),
|
||||
(implicit EFLAGS)),
|
||||
(ADD8rm GR8:$src1, addr:$src2)>;
|
||||
def : Pat<(parallel (X86add_ovf GR16:$src1, (load addr:$src2)),
|
||||
def : Pat<(parallel (X86add_flag GR16:$src1, (loadi16 addr:$src2)),
|
||||
(implicit EFLAGS)),
|
||||
(ADD16rm GR16:$src1, addr:$src2)>;
|
||||
def : Pat<(parallel (X86add_ovf GR32:$src1, (load addr:$src2)),
|
||||
def : Pat<(parallel (X86add_flag GR32:$src1, (loadi32 addr:$src2)),
|
||||
(implicit EFLAGS)),
|
||||
(ADD32rm GR32:$src1, addr:$src2)>;
|
||||
|
||||
// Register-Integer Addition with Overflow
|
||||
def : Pat<(parallel (X86add_ovf GR8:$src1, imm:$src2),
|
||||
// Register-Integer Addition with EFLAGS result
|
||||
def : Pat<(parallel (X86add_flag GR8:$src1, imm:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(ADD8ri GR8:$src1, imm:$src2)>;
|
||||
|
||||
// Register-Integer Addition with Overflow
|
||||
def : Pat<(parallel (X86add_ovf GR16:$src1, imm:$src2),
|
||||
// Register-Integer Addition with EFLAGS result
|
||||
def : Pat<(parallel (X86add_flag GR16:$src1, imm:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(ADD16ri GR16:$src1, imm:$src2)>;
|
||||
def : Pat<(parallel (X86add_ovf GR32:$src1, imm:$src2),
|
||||
def : Pat<(parallel (X86add_flag GR32:$src1, imm:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(ADD32ri GR32:$src1, imm:$src2)>;
|
||||
def : Pat<(parallel (X86add_ovf GR16:$src1, i16immSExt8:$src2),
|
||||
def : Pat<(parallel (X86add_flag GR16:$src1, i16immSExt8:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
|
||||
def : Pat<(parallel (X86add_ovf GR32:$src1, i32immSExt8:$src2),
|
||||
def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
|
||||
|
||||
// Memory-Register Addition with Overflow
|
||||
def : Pat<(parallel (store (X86add_ovf (load addr:$dst), GR8:$src2),
|
||||
// Memory-Register Addition with EFLAGS result
|
||||
def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2),
|
||||
addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(ADD8mr addr:$dst, GR8:$src2)>;
|
||||
def : Pat<(parallel (store (X86add_ovf (load addr:$dst), GR16:$src2),
|
||||
def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), GR16:$src2),
|
||||
addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(ADD16mr addr:$dst, GR16:$src2)>;
|
||||
def : Pat<(parallel (store (X86add_ovf (load addr:$dst), GR32:$src2),
|
||||
def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), GR32:$src2),
|
||||
addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(ADD32mr addr:$dst, GR32:$src2)>;
|
||||
def : Pat<(parallel (store (X86add_ovf (loadi8 addr:$dst), imm:$src2),
|
||||
def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), imm:$src2),
|
||||
addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(ADD8mi addr:$dst, imm:$src2)>;
|
||||
def : Pat<(parallel (store (X86add_ovf (loadi16 addr:$dst), imm:$src2),
|
||||
def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), imm:$src2),
|
||||
addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(ADD16mi addr:$dst, imm:$src2)>;
|
||||
def : Pat<(parallel (store (X86add_ovf (loadi32 addr:$dst), imm:$src2),
|
||||
def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), imm:$src2),
|
||||
addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(ADD32mi addr:$dst, imm:$src2)>;
|
||||
def : Pat<(parallel (store (X86add_ovf (load addr:$dst), i16immSExt8:$src2),
|
||||
def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), i16immSExt8:$src2),
|
||||
addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(ADD16mi8 addr:$dst, i16immSExt8:$src2)>;
|
||||
def : Pat<(parallel (store (X86add_ovf (load addr:$dst), i32immSExt8:$src2),
|
||||
def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2),
|
||||
addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
|
||||
|
||||
// Register-Register Subtraction with Overflow
|
||||
def : Pat<(parallel (X86sub_ovf GR8:$src1, GR8:$src2),
|
||||
// Register-Register Subtraction with EFLAGS result
|
||||
def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(SUB8rr GR8:$src1, GR8:$src2)>;
|
||||
def : Pat<(parallel (X86sub_ovf GR16:$src1, GR16:$src2),
|
||||
def : Pat<(parallel (X86sub_flag GR16:$src1, GR16:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(SUB16rr GR16:$src1, GR16:$src2)>;
|
||||
def : Pat<(parallel (X86sub_ovf GR32:$src1, GR32:$src2),
|
||||
def : Pat<(parallel (X86sub_flag GR32:$src1, GR32:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(SUB32rr GR32:$src1, GR32:$src2)>;
|
||||
|
||||
// Register-Memory Subtraction with Overflow
|
||||
def : Pat<(parallel (X86sub_ovf GR8:$src1, (load addr:$src2)),
|
||||
// Register-Memory Subtraction with EFLAGS result
|
||||
def : Pat<(parallel (X86sub_flag GR8:$src1, (loadi8 addr:$src2)),
|
||||
(implicit EFLAGS)),
|
||||
(SUB8rm GR8:$src1, addr:$src2)>;
|
||||
def : Pat<(parallel (X86sub_ovf GR16:$src1, (load addr:$src2)),
|
||||
def : Pat<(parallel (X86sub_flag GR16:$src1, (loadi16 addr:$src2)),
|
||||
(implicit EFLAGS)),
|
||||
(SUB16rm GR16:$src1, addr:$src2)>;
|
||||
def : Pat<(parallel (X86sub_ovf GR32:$src1, (load addr:$src2)),
|
||||
def : Pat<(parallel (X86sub_flag GR32:$src1, (loadi32 addr:$src2)),
|
||||
(implicit EFLAGS)),
|
||||
(SUB32rm GR32:$src1, addr:$src2)>;
|
||||
|
||||
// Register-Integer Subtraction with Overflow
|
||||
def : Pat<(parallel (X86sub_ovf GR8:$src1, imm:$src2),
|
||||
// Register-Integer Subtraction with EFLAGS result
|
||||
def : Pat<(parallel (X86sub_flag GR8:$src1, imm:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(SUB8ri GR8:$src1, imm:$src2)>;
|
||||
def : Pat<(parallel (X86sub_ovf GR16:$src1, imm:$src2),
|
||||
def : Pat<(parallel (X86sub_flag GR16:$src1, imm:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(SUB16ri GR16:$src1, imm:$src2)>;
|
||||
def : Pat<(parallel (X86sub_ovf GR32:$src1, imm:$src2),
|
||||
def : Pat<(parallel (X86sub_flag GR32:$src1, imm:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(SUB32ri GR32:$src1, imm:$src2)>;
|
||||
def : Pat<(parallel (X86sub_ovf GR16:$src1, i16immSExt8:$src2),
|
||||
def : Pat<(parallel (X86sub_flag GR16:$src1, i16immSExt8:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
|
||||
def : Pat<(parallel (X86sub_ovf GR32:$src1, i32immSExt8:$src2),
|
||||
def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
|
||||
|
||||
// Memory-Register Subtraction with Overflow
|
||||
def : Pat<(parallel (store (X86sub_ovf (load addr:$dst), GR8:$src2),
|
||||
// Memory-Register Subtraction with EFLAGS result
|
||||
def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2),
|
||||
addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(SUB8mr addr:$dst, GR8:$src2)>;
|
||||
def : Pat<(parallel (store (X86sub_ovf (load addr:$dst), GR16:$src2),
|
||||
def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), GR16:$src2),
|
||||
addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(SUB16mr addr:$dst, GR16:$src2)>;
|
||||
def : Pat<(parallel (store (X86sub_ovf (load addr:$dst), GR32:$src2),
|
||||
def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), GR32:$src2),
|
||||
addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(SUB32mr addr:$dst, GR32:$src2)>;
|
||||
|
||||
// Memory-Integer Subtraction with Overflow
|
||||
def : Pat<(parallel (store (X86sub_ovf (loadi8 addr:$dst), imm:$src2),
|
||||
// Memory-Integer Subtraction with EFLAGS result
|
||||
def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), imm:$src2),
|
||||
addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(SUB8mi addr:$dst, imm:$src2)>;
|
||||
def : Pat<(parallel (store (X86sub_ovf (loadi16 addr:$dst), imm:$src2),
|
||||
def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), imm:$src2),
|
||||
addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(SUB16mi addr:$dst, imm:$src2)>;
|
||||
def : Pat<(parallel (store (X86sub_ovf (loadi32 addr:$dst), imm:$src2),
|
||||
def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), imm:$src2),
|
||||
addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(SUB32mi addr:$dst, imm:$src2)>;
|
||||
def : Pat<(parallel (store (X86sub_ovf (load addr:$dst), i16immSExt8:$src2),
|
||||
def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), i16immSExt8:$src2),
|
||||
addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(SUB16mi8 addr:$dst, i16immSExt8:$src2)>;
|
||||
def : Pat<(parallel (store (X86sub_ovf (load addr:$dst), i32immSExt8:$src2),
|
||||
def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2),
|
||||
addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
|
||||
|
||||
|
||||
// Register-Register Signed Integer Multiply with Overflow
|
||||
def : Pat<(parallel (X86smul_ovf GR16:$src1, GR16:$src2),
|
||||
// Register-Register Signed Integer Multiply with EFLAGS result
|
||||
def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(IMUL16rr GR16:$src1, GR16:$src2)>;
|
||||
def : Pat<(parallel (X86smul_ovf GR32:$src1, GR32:$src2),
|
||||
def : Pat<(parallel (X86smul_flag GR32:$src1, GR32:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(IMUL32rr GR32:$src1, GR32:$src2)>;
|
||||
|
||||
// Register-Memory Signed Integer Multiply with Overflow
|
||||
def : Pat<(parallel (X86smul_ovf GR16:$src1, (load addr:$src2)),
|
||||
// Register-Memory Signed Integer Multiply with EFLAGS result
|
||||
def : Pat<(parallel (X86smul_flag GR16:$src1, (loadi16 addr:$src2)),
|
||||
(implicit EFLAGS)),
|
||||
(IMUL16rm GR16:$src1, addr:$src2)>;
|
||||
def : Pat<(parallel (X86smul_ovf GR32:$src1, (load addr:$src2)),
|
||||
def : Pat<(parallel (X86smul_flag GR32:$src1, (loadi32 addr:$src2)),
|
||||
(implicit EFLAGS)),
|
||||
(IMUL32rm GR32:$src1, addr:$src2)>;
|
||||
|
||||
// Register-Integer Signed Integer Multiply with Overflow
|
||||
def : Pat<(parallel (X86smul_ovf GR16:$src1, imm:$src2),
|
||||
// Register-Integer Signed Integer Multiply with EFLAGS result
|
||||
def : Pat<(parallel (X86smul_flag GR16:$src1, imm:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(IMUL16rri GR16:$src1, imm:$src2)>;
|
||||
def : Pat<(parallel (X86smul_ovf GR32:$src1, imm:$src2),
|
||||
def : Pat<(parallel (X86smul_flag GR32:$src1, imm:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(IMUL32rri GR32:$src1, imm:$src2)>;
|
||||
def : Pat<(parallel (X86smul_ovf GR16:$src1, i16immSExt8:$src2),
|
||||
def : Pat<(parallel (X86smul_flag GR16:$src1, i16immSExt8:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
|
||||
def : Pat<(parallel (X86smul_ovf GR32:$src1, i32immSExt8:$src2),
|
||||
def : Pat<(parallel (X86smul_flag GR32:$src1, i32immSExt8:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
|
||||
|
||||
// Memory-Integer Signed Integer Multiply with Overflow
|
||||
def : Pat<(parallel (X86smul_ovf (load addr:$src1), imm:$src2),
|
||||
// Memory-Integer Signed Integer Multiply with EFLAGS result
|
||||
def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), imm:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(IMUL16rmi addr:$src1, imm:$src2)>;
|
||||
def : Pat<(parallel (X86smul_ovf (load addr:$src1), imm:$src2),
|
||||
def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), imm:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(IMUL32rmi addr:$src1, imm:$src2)>;
|
||||
def : Pat<(parallel (X86smul_ovf (load addr:$src1), i16immSExt8:$src2),
|
||||
def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), i16immSExt8:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
|
||||
def : Pat<(parallel (X86smul_ovf (load addr:$src1), i32immSExt8:$src2),
|
||||
def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), i32immSExt8:$src2),
|
||||
(implicit EFLAGS)),
|
||||
(IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
|
||||
|
||||
// Optimize multiple with overflow by 2.
|
||||
// Optimize multiply by 2 with EFLAGS result.
|
||||
let AddedComplexity = 2 in {
|
||||
def : Pat<(parallel (X86smul_ovf GR16:$src1, 2),
|
||||
def : Pat<(parallel (X86smul_flag GR16:$src1, 2),
|
||||
(implicit EFLAGS)),
|
||||
(ADD16rr GR16:$src1, GR16:$src1)>;
|
||||
|
||||
def : Pat<(parallel (X86smul_ovf GR32:$src1, 2),
|
||||
def : Pat<(parallel (X86smul_flag GR32:$src1, 2),
|
||||
(implicit EFLAGS)),
|
||||
(ADD32rr GR32:$src1, GR32:$src1)>;
|
||||
}
|
||||
|
||||
// INC and DEC with EFLAGS result. Note that these do not set CF.
|
||||
def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)),
|
||||
(INC8r GR8:$src)>;
|
||||
def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(INC8m addr:$dst)>;
|
||||
def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)),
|
||||
(DEC8r GR8:$src)>;
|
||||
def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(DEC8m addr:$dst)>;
|
||||
|
||||
def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
|
||||
(INC16r GR16:$src)>;
|
||||
def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(INC16m addr:$dst)>;
|
||||
def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
|
||||
(DEC16r GR16:$src)>;
|
||||
def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(DEC16m addr:$dst)>;
|
||||
|
||||
def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
|
||||
(INC32r GR32:$src)>;
|
||||
def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(INC32m addr:$dst)>;
|
||||
def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
|
||||
(DEC32r GR32:$src)>;
|
||||
def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(DEC32m addr:$dst)>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Floating Point Stack Support
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
22
test/CodeGen/X86/peep-test.ll
Normal file
22
test/CodeGen/X86/peep-test.ll
Normal file
@ -0,0 +1,22 @@
|
||||
; RUN: llvm-as < %s | llc -march=x86-64 > %t
|
||||
; RUN: not grep cmp %t
|
||||
; RUN: not grep test %t
|
||||
|
||||
define void @loop(i64 %n, double* nocapture %d) nounwind {
|
||||
entry:
|
||||
br label %bb
|
||||
|
||||
bb:
|
||||
%indvar = phi i64 [ %n, %entry ], [ %indvar.next, %bb ]
|
||||
%i.03 = add i64 %indvar, %n
|
||||
%0 = getelementptr double* %d, i64 %i.03
|
||||
%1 = load double* %0, align 8
|
||||
%2 = mul double %1, 3.000000e+00
|
||||
store double %2, double* %0, align 8
|
||||
%indvar.next = add i64 %indvar, 1
|
||||
%exitcond = icmp eq i64 %indvar.next, 0
|
||||
br i1 %exitcond, label %return, label %bb
|
||||
|
||||
return:
|
||||
ret void
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user