mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-18 12:29:27 +00:00
fcopysign and get rid of dsnode cruft. custom PA runtimes make this better in some senses
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26641 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth
parent
97d74aac35
commit
13beebb25b
@ -26,12 +26,6 @@
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using namespace llvm;
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namespace llvm {
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cl::opt<bool> EnableAlphaLSMark("enable-alpha-lsmark",
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cl::desc("Emit symbols to correlate Mem ops to LLVM Values"),
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cl::Hidden);
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}
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/// AddLiveIn - This helper function adds the specified physical register to the
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/// MachineFunction as a live in value. It also creates a corresponding virtual
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/// register for it.
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@ -71,20 +65,6 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
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setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
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if (EnableAlphaLSMark) {
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setOperationAction(ISD::LOAD, MVT::i64, Custom);
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setOperationAction(ISD::LOAD, MVT::f64, Custom);
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setOperationAction(ISD::LOAD, MVT::f32, Custom);
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setOperationAction(ISD::ZEXTLOAD, MVT::i8, Custom);
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setOperationAction(ISD::ZEXTLOAD, MVT::i16, Custom);
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setOperationAction(ISD::SEXTLOAD, MVT::i32, Custom);
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setOperationAction(ISD::EXTLOAD, MVT::i8, Custom);
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setOperationAction(ISD::EXTLOAD, MVT::i16, Custom);
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setOperationAction(ISD::EXTLOAD, MVT::i32, Custom);
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}
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setOperationAction(ISD::FREM, MVT::f32, Expand);
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setOperationAction(ISD::FREM, MVT::f64, Expand);
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@ -175,18 +155,6 @@ const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case AlphaISD::GlobalBaseReg: return "Alpha::GlobalBaseReg";
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case AlphaISD::CALL: return "Alpha::CALL";
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case AlphaISD::DivCall: return "Alpha::DivCall";
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case AlphaISD::LDQ_: return "Alpha::LDQ_";
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case AlphaISD::LDT_: return "Alpha::LDT_";
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case AlphaISD::LDS_: return "Alpha::LDS_";
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case AlphaISD::LDL_: return "Alpha::LDL_";
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case AlphaISD::LDWU_: return "Alpha::LDWU_";
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case AlphaISD::LDBU_: return "Alpha::LDBU_";
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case AlphaISD::STQ_: return "Alpha::STQ_";
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case AlphaISD::STT_: return "Alpha::STT_";
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case AlphaISD::STS_: return "Alpha::STS_";
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case AlphaISD::STL_: return "Alpha::STL_";
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case AlphaISD::STW_: return "Alpha::STW_";
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case AlphaISD::STB_: return "Alpha::STB_";
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}
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}
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@ -395,48 +363,6 @@ void AlphaTargetLowering::restoreRA(MachineBasicBlock* BB)
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BuildMI(BB, Alpha::BIS, 2, Alpha::R26).addReg(RA).addReg(RA);
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}
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static void getValueInfo(const Value* v, int& type, int& fun, int& offset)
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{
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fun = type = offset = 0;
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if (v == NULL) {
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type = 0;
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} else if (const GlobalValue* GV = dyn_cast<GlobalValue>(v)) {
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type = 1;
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const Module* M = GV->getParent();
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for(Module::const_global_iterator ii = M->global_begin(); &*ii != GV; ++ii)
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++offset;
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} else if (const Argument* Arg = dyn_cast<Argument>(v)) {
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type = 2;
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const Function* F = Arg->getParent();
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const Module* M = F->getParent();
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for(Module::const_iterator ii = M->begin(); &*ii != F; ++ii)
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++fun;
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for(Function::const_arg_iterator ii = F->arg_begin(); &*ii != Arg; ++ii)
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++offset;
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} else if (const Instruction* I = dyn_cast<Instruction>(v)) {
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assert(dyn_cast<PointerType>(I->getType()));
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type = 3;
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const BasicBlock* bb = I->getParent();
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const Function* F = bb->getParent();
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const Module* M = F->getParent();
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for(Module::const_iterator ii = M->begin(); &*ii != F; ++ii)
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++fun;
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for(Function::const_iterator ii = F->begin(); &*ii != bb; ++ii)
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offset += ii->size();
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for(BasicBlock::const_iterator ii = bb->begin(); &*ii != I; ++ii)
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++offset;
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} else if (const Constant* C = dyn_cast<Constant>(v)) {
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//Don't know how to look these up yet
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type = 0;
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} else {
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assert(0 && "Error in value marking");
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}
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//type = 4: register spilling
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//type = 5: global address loading or constant loading
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}
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static int getUID()
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{
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static int id = 0;
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@ -535,97 +461,6 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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}
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break;
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case ISD::LOAD:
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case ISD::SEXTLOAD:
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case ISD::ZEXTLOAD:
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case ISD::EXTLOAD:
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{
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SDOperand Chain = Op.getOperand(0);
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SDOperand Address = Op.getOperand(1);
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unsigned Opc;
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unsigned opcode = Op.getOpcode();
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if (opcode == ISD::LOAD)
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switch (Op.Val->getValueType(0)) {
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default: Op.Val->dump(); assert(0 && "Bad load!");
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case MVT::i64: Opc = AlphaISD::LDQ_; break;
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case MVT::f64: Opc = AlphaISD::LDT_; break;
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case MVT::f32: Opc = AlphaISD::LDS_; break;
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}
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else
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switch (cast<VTSDNode>(Op.getOperand(3))->getVT()) {
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default: Op.Val->dump(); assert(0 && "Bad sign extend!");
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case MVT::i32: Opc = AlphaISD::LDL_;
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assert(opcode != ISD::ZEXTLOAD && "Not sext"); break;
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case MVT::i16: Opc = AlphaISD::LDWU_;
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assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
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case MVT::i1: //FIXME: Treat i1 as i8 since there are problems otherwise
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case MVT::i8: Opc = AlphaISD::LDBU_;
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assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
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}
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int i, j, k;
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getValueInfo(dyn_cast<SrcValueSDNode>(Op.getOperand(2))->getValue(), i, j, k);
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SDOperand Zero = DAG.getConstant(0, MVT::i64);
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std::vector<MVT::ValueType> VTS;
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VTS.push_back(Op.Val->getValueType(0));
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VTS.push_back(MVT::Other);
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std::vector<SDOperand> ARGS;
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ARGS.push_back(Chain);
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ARGS.push_back(Zero);
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ARGS.push_back(Address);
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ARGS.push_back(DAG.getConstant(i, MVT::i64));
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ARGS.push_back(DAG.getConstant(j, MVT::i64));
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ARGS.push_back(DAG.getConstant(k, MVT::i64));
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ARGS.push_back(DAG.getConstant(getUID(), MVT::i64));
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return DAG.getNode(Opc, VTS, ARGS);
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}
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case ISD::TRUNCSTORE:
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case ISD::STORE:
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{
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SDOperand Chain = Op.getOperand(0);
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SDOperand Value = Op.getOperand(1);
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SDOperand Address = Op.getOperand(2);
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unsigned Opc;
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unsigned opcode = Op.getOpcode();
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if (opcode == ISD::STORE) {
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switch(Value.getValueType()) {
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default: assert(0 && "unknown Type in store");
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case MVT::i64: Opc = AlphaISD::STQ_; break;
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case MVT::f64: Opc = AlphaISD::STT_; break;
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case MVT::f32: Opc = AlphaISD::STS_; break;
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}
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} else { //ISD::TRUNCSTORE
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switch(cast<VTSDNode>(Op.getOperand(4))->getVT()) {
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default: assert(0 && "unknown Type in store");
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case MVT::i8: Opc = AlphaISD::STB_; break;
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case MVT::i16: Opc = AlphaISD::STW_; break;
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case MVT::i32: Opc = AlphaISD::STL_; break;
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}
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}
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int i, j, k;
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getValueInfo(cast<SrcValueSDNode>(Op.getOperand(3))->getValue(), i, j, k);
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SDOperand Zero = DAG.getConstant(0, MVT::i64);
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std::vector<MVT::ValueType> VTS;
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VTS.push_back(MVT::Other);
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std::vector<SDOperand> ARGS;
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ARGS.push_back(Chain);
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ARGS.push_back(Value);
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ARGS.push_back(Zero);
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ARGS.push_back(Address);
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ARGS.push_back(DAG.getConstant(i, MVT::i64));
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ARGS.push_back(DAG.getConstant(j, MVT::i64));
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ARGS.push_back(DAG.getConstant(k, MVT::i64));
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ARGS.push_back(DAG.getConstant(getUID(), MVT::i64));
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return DAG.getNode(Opc, VTS, ARGS);
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}
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case ISD::VAARG: {
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SDOperand Chain = Op.getOperand(0);
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SDOperand VAListP = Op.getOperand(1);
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@ -19,13 +19,6 @@ include "AlphaInstrFormats.td"
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def SDTFPUnaryOpUnC : SDTypeProfile<1, 1, [
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SDTCisFP<1>, SDTCisFP<0>
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]>;
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def SDTLoadA : SDTypeProfile<1, 6, [ // load
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SDTCisInt<1>, SDTCisPtrTy<2>, SDTCisInt<3>, SDTCisInt<4>, SDTCisInt<5>, SDTCisInt<6>
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]>;
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def SDTStoreA : SDTypeProfile<0, 7, [ // load
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SDTCisInt<1>, SDTCisPtrTy<2>, SDTCisInt<3>, SDTCisInt<4>, SDTCisInt<5>, SDTCisInt<6>
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]>;
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def Alpha_itoft : SDNode<"AlphaISD::ITOFT_", SDTIntToFPOp, []>;
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def Alpha_ftoit : SDNode<"AlphaISD::FTOIT_", SDTFPToIntOp, []>;
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def Alpha_cvtqt : SDNode<"AlphaISD::CVTQT_", SDTFPUnaryOpUnC, []>;
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@ -34,18 +27,6 @@ def Alpha_cvttq : SDNode<"AlphaISD::CVTTQ_" , SDTFPUnaryOp, []>;
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def Alpha_gprello : SDNode<"AlphaISD::GPRelLo", SDTIntBinOp, []>;
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def Alpha_gprelhi : SDNode<"AlphaISD::GPRelHi", SDTIntBinOp, []>;
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def Alpha_rellit : SDNode<"AlphaISD::RelLit", SDTIntBinOp, []>;
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def Alpha_ldq : SDNode<"AlphaISD::LDQ_", SDTLoadA, [SDNPHasChain]>;
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def Alpha_ldt : SDNode<"AlphaISD::LDT_", SDTLoadA, [SDNPHasChain]>;
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def Alpha_lds : SDNode<"AlphaISD::LDS_", SDTLoadA, [SDNPHasChain]>;
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def Alpha_ldl : SDNode<"AlphaISD::LDL_", SDTLoadA, [SDNPHasChain]>;
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def Alpha_ldwu : SDNode<"AlphaISD::LDWU_", SDTLoadA, [SDNPHasChain]>;
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def Alpha_ldbu : SDNode<"AlphaISD::LDBU_", SDTLoadA, [SDNPHasChain]>;
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def Alpha_stq : SDNode<"AlphaISD::STQ_", SDTStoreA, [SDNPHasChain]>;
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def Alpha_stl : SDNode<"AlphaISD::STL_", SDTStoreA, [SDNPHasChain]>;
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def Alpha_stw : SDNode<"AlphaISD::STW_", SDTStoreA, [SDNPHasChain]>;
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def Alpha_stb : SDNode<"AlphaISD::STB_", SDTStoreA, [SDNPHasChain]>;
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def Alpha_sts : SDNode<"AlphaISD::STS_", SDTStoreA, [SDNPHasChain]>;
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def Alpha_stt : SDNode<"AlphaISD::STT_", SDTStoreA, [SDNPHasChain]>;
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// These are target-independent nodes, but have target-specific formats.
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def SDT_AlphaCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i64> ]>;
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@ -569,38 +550,6 @@ def : Pat<(Alpha_rellit texternalsym:$ext, GPRC:$RB),
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(LDQl texternalsym:$ext, GPRC:$RB)>;
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//Various tracked versions
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let OperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB,
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s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m) in {
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def LDQlbl : MForm<0x29, 0, 1, "LSMARKER$$$i$$$j$$$k$$$m:\n\t ldq $RA,$DISP($RB)",
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[(set GPRC:$RA, (Alpha_ldq imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m))]>;
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def LDLlbl : MForm<0x28, 0, 1, "LSMARKER$$$i$$$j$$$k$$$m:\n\t ldl $RA,$DISP($RB)",
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[(set GPRC:$RA, (Alpha_ldl imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m))]>;
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def LDBUlbl : MForm<0x0A, 0, 1, "LSMARKER$$$i$$$j$$$k$$$m:\n\t ldbu $RA,$DISP($RB)",
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[(set GPRC:$RA, (Alpha_ldwu imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m))]>;
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def LDWUlbl : MForm<0x0C, 0, 1, "LSMARKER$$$i$$$j$$$k$$$m:\n\t ldwu $RA,$DISP($RB)",
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[(set GPRC:$RA, (Alpha_ldbu imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m))]>;
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def STBlbl : MForm<0x0E, 1, 0, "LSMARKER$$$i$$$j$$$k$$$m:\n\t stb $RA,$DISP($RB)",
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[(Alpha_stb GPRC:$RA, imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m)]>;
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def STWlbl : MForm<0x0D, 1, 0, "LSMARKER$$$i$$$j$$$k$$$m:\n\t stw $RA,$DISP($RB)",
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[(Alpha_stw GPRC:$RA, imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m)]>;
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def STLlbl : MForm<0x2C, 1, 0, "LSMARKER$$$i$$$j$$$k$$$m:\n\t stl $RA,$DISP($RB)",
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[(Alpha_stl GPRC:$RA, imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m)]>;
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def STQlbl : MForm<0x2D, 1, 0, "LSMARKER$$$i$$$j$$$k$$$m:\n\t stq $RA,$DISP($RB)",
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[(Alpha_stq GPRC:$RA, imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m)]>;
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}
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let OperandList = (ops F8RC:$RA, s64imm:$DISP, GPRC:$RB,
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s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m) in
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def LDTlbl : MForm<0x29, 0, 1, "LSMARKER$$$i$$$j$$$k$$$m:\n\t ldt $RA,$DISP($RB)",
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[(set F8RC:$RA, (Alpha_ldt imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m))]>;
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let OperandList = (ops F4RC:$RA, s64imm:$DISP, GPRC:$RB,
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s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m) in
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def LDSlbl : MForm<0x29, 0, 1, "LSMARKER$$$i$$$j$$$k$$$m:\n\t lds $RA,$DISP($RB)",
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[(set F4RC:$RA, (Alpha_lds imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m))]>;
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def RPCC : MfcForm<0x18, 0xC000, "rpcc $RA">; //Read process cycle counter
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//Basic Floating point ops
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@ -621,9 +570,12 @@ def DIVS : FPForm<0x16, 0x583, "divs/su $RA,$RB,$RC",
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def MULS : FPForm<0x16, 0x582, "muls/su $RA,$RB,$RC",
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[(set F4RC:$RC, (fmul F4RC:$RA, F4RC:$RB))]>;
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def CPYSS : FPForm<0x17, 0x020, "cpys $RA,$RB,$RC",[]>; //Copy sign
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def CPYSS : FPForm<0x17, 0x020, "cpys $RA,$RB,$RC",
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[(set F4RC:$RC, (fcopysign F4RC:$RA, F4RC:$RB))]>;
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def CPYSES : FPForm<0x17, 0x022, "cpyse $RA,$RB,$RC",[]>; //Copy sign and exponent
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def CPYSNS : FPForm<0x17, 0x021, "cpysn $RA,$RB,$RC",[]>; //Copy sign negate
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//FIXME: This might be legalized in the oposite manner
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def CPYSNS : FPForm<0x17, 0x021, "cpysn $RA,$RB,$RC",
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[(set F4RC:$RC, (fneg (fcopysign F4RC:$RA, F4RC:$RB)))]>;
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}
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//Doubles
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@ -642,9 +594,12 @@ def DIVT : FPForm<0x16, 0x5A3, "divt/su $RA,$RB,$RC",
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def MULT : FPForm<0x16, 0x5A2, "mult/su $RA,$RB,$RC",
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[(set F8RC:$RC, (fmul F8RC:$RA, F8RC:$RB))]>;
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def CPYST : FPForm<0x17, 0x020, "cpys $RA,$RB,$RC",[]>; //Copy sign
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def CPYST : FPForm<0x17, 0x020, "cpys $RA,$RB,$RC",
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[(set F8RC:$RC, (fcopysign F8RC:$RA, F8RC:$RB))]>;
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def CPYSET : FPForm<0x17, 0x022, "cpyse $RA,$RB,$RC",[]>; //Copy sign and exponent
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def CPYSNT : FPForm<0x17, 0x021, "cpysn $RA,$RB,$RC",[]>; //Copy sign negate
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//FIXME: This might be legalized in the oposite manner
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def CPYSNT : FPForm<0x17, 0x021, "cpysn $RA,$RB,$RC",
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[(set F8RC:$RC, (fneg (fcopysign F8RC:$RA, F8RC:$RB)))]>;
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def CMPTEQ : FPForm<0x16, 0x5A5, "cmpteq/su $RA,$RB,$RC", []>;
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// [(set F8RC:$RC, (seteq F8RC:$RA, F8RC:$RB))]>;
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@ -895,6 +850,11 @@ def : Pat<(fneg F8RC:$RB),
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(CPYSNT F8RC:$RB, F8RC:$RB)>;
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def : Pat<(fneg F4RC:$RB),
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(CPYSNS F4RC:$RB, F4RC:$RB)>;
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def : Pat<(fcopysign (fneg F4RC:$A), F4RC:$B),
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(CPYSNS F4RC:$A, F4RC:$B)>;
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def : Pat<(fcopysign (fneg F8RC:$A), F8RC:$B),
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(CPYSNT F8RC:$A, F8RC:$B)>;
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//Yes, signed multiply high is ugly
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def : Pat<(mulhs GPRC:$RA, GPRC:$RB),
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(SUBQ (UMULH GPRC:$RA, GPRC:$RB), (ADDQ (CMOVGE GPRC:$RB, R31, GPRC:$RA),
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