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Merging r227430:

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r227430 | vmedic | 2015-01-29 11:33:41 +0000 (Thu, 29 Jan 2015) | 1 line

[Mips][Disassembler] When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235864 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
2015-04-27 11:59:49 +00:00
parent e2940c6516
commit 144749b59b
8 changed files with 31 additions and 7 deletions
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lib/Target/Mips/Disassembler/MipsDisassembler.cpp
+22
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@@ -259,6 +259,11 @@ static DecodeStatus DecodeCacheOp(MCInst &Inst,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeCacheOpR6(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
unsigned Insn,
uint64_t Address,
@@ -1122,6 +1127,23 @@ static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
return MCDisassembler::Success;
}
static DecodeStatus DecodeCacheOpR6(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
int Offset = fieldFromInstruction(Insn, 7, 9);
unsigned Hint = fieldFromInstruction(Insn, 16, 5);
unsigned Base = fieldFromInstruction(Insn, 21, 5);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
Inst.addOperand(MCOperand::CreateReg(Base));
Inst.addOperand(MCOperand::CreateImm(Offset));
Inst.addOperand(MCOperand::CreateImm(Hint));
return MCDisassembler::Success;
}
static DecodeStatus DecodeSyncI(MCInst &Inst,
unsigned Insn,
uint64_t Address,
lib/Target/Mips/Mips32r6InstrInfo.td
+1
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@@ -549,6 +549,7 @@ class CACHE_HINT_DESC<string instr_asm, Operand MemOpnd,
dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
list<dag> Pattern = [];
string DecoderMethod = "DecodeCacheOpR6";
}
class CACHE_DESC : CACHE_HINT_DESC<"cache", mem_simm9, GPR32Opnd>;
test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
+2
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@@ -144,3 +144,5 @@
0x30 0x81 0x79 0x49 # CHECK: swc2 $25, 304($16)
0x00 0x01 0x05 0xf8 # CHECK: jialc $5, 256
0x00 0x01 0x05 0xd8 # CHECK: jic $5, 256
0x25 0x04 0xa1 0x7c # CHECK: cache 1, 8($5)
0x35 0x04 0xa1 0x7c # CHECK: pref 1, 8($5
test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
+2 -1
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@@ -144,4 +144,5 @@
0x49 0x79 0x81 0x30 # CHECK: swc2 $25, 304($16)
0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256
0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256
0x7c 0xa1 0x04 0x25 # CHECK: cache 1, 8($5)
0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5)
test/MC/Disassembler/Mips/mips32r6/valid-xfail-mips32r6.txt
-2
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@@ -13,5 +13,3 @@
0x60 0xc0 0x00 0x40 # CHECK: bnec $6, $zero, 256
0x60 0xa0 0x00 0x40 # CHECK: bnec $5, $zero, 256
0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 256
0x7c 0xa1 0x04 0x25 # CHECK: cache 1, 8($5)
0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5)
test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
+2 -1
View File
@@ -162,4 +162,5 @@
0x30 0x81 0x79 0x49 # CHECK: swc2 $25, 304($16)
0x00 0x01 0x05 0xf8 # CHECK: jialc $5, 256
0x00 0x01 0x05 0xd8 # CHECK: jic $5, 256
0x25 0x04 0xa1 0x7c # CHECK: cache 1, 8($5)
0x35 0x04 0xa1 0x7c # CHECK: pref 1, 8($5)
test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
+2 -1
View File
@@ -162,4 +162,5 @@
0x49 0x79 0x81 0x30 # CHECK: swc2 $25, 304($16)
0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256
0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256
0x7c 0xa1 0x04 0x25 # CHECK: cache 1, 8($5)
0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5)
test/MC/Disassembler/Mips/mips64r6/valid-xfail-mips64r6.txt
-2
View File
@@ -13,8 +13,6 @@
0x60 0xc0 0x00 0x40 # CHECK: bnec $6, $zero, 256
0x60 0xa0 0x00 0x40 # CHECK: bnec $5, $zero, 256
0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 256
0x7c 0xa1 0x04 0x25 # CHECK: cache 1, 8($5)
0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5)
0x64 0x58 0x46 0x9f # CHECK: daddiu $24, $2, 18079
0x66 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943
0x65 0x6f 0xec 0x5f # CHECK: daddiu $15, $11, -5025