mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 21:29:20 +00:00
Properly split f32 and f64 into separate register classes for scalar sse fp
fixing a bunch of nasty hackery git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23735 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
e0de44adba
commit
14e2cf62f4
@ -184,8 +184,8 @@ namespace {
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if (X86ScalarSSE) {
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// Set up the FP register classes.
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addRegisterClass(MVT::f32, X86::RXMMRegisterClass);
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addRegisterClass(MVT::f64, X86::RXMMRegisterClass);
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addRegisterClass(MVT::f32, X86::V4F4RegisterClass);
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addRegisterClass(MVT::f64, X86::V2F8RegisterClass);
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// SSE has no load+extend ops
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setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
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@ -4192,10 +4192,10 @@ void ISel::Select(SDOperand N) {
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case MVT::i8: Opc = X86::MOV8rr; break;
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case MVT::i16: Opc = X86::MOV16rr; break;
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case MVT::i32: Opc = X86::MOV32rr; break;
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case MVT::f32: Opc = X86::MOVAPSrr; break;
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case MVT::f32: Opc = X86::MOVSSrr; break;
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case MVT::f64:
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if (X86ScalarSSE) {
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Opc = X86::MOVAPDrr;
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Opc = X86::MOVSDrr;
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} else {
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Opc = X86::FpMOV;
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ContainsFPCode = true;
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@ -28,7 +28,7 @@ bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
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unsigned& destReg) const {
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MachineOpCode oc = MI.getOpcode();
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if (oc == X86::MOV8rr || oc == X86::MOV16rr || oc == X86::MOV32rr ||
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oc == X86::FpMOV || oc == X86::MOVAPDrr || oc == X86::MOVAPSrr) {
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oc == X86::FpMOV || oc == X86::MOVSSrr || oc == X86::MOVSDrr) {
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assert(MI.getNumOperands() == 2 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() &&
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@ -1408,142 +1408,134 @@ def MOVZX32rm16: I<0xB7, MRMSrcMem, (ops R32:$dst, i16mem:$src),
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// XMM Floating point support (requires SSE2)
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//===----------------------------------------------------------------------===//
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def MOVSSrm : I<0x10, MRMSrcMem, (ops RXMM:$dst, f32mem:$src),
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def MOVSSrr : I<0x10, MRMSrcReg, (ops V4F4:$dst, V4F4:$src),
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"movss {$src, $dst|$dst, $src}">, XS;
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def MOVSSmr : I<0x11, MRMDestMem, (ops f32mem:$dst, RXMM:$src),
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def MOVSSrm : I<0x10, MRMSrcMem, (ops V4F4:$dst, f32mem:$src),
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"movss {$src, $dst|$dst, $src}">, XS;
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def MOVSDrm : I<0x10, MRMSrcMem, (ops RXMM:$dst, f64mem:$src),
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def MOVSSmr : I<0x11, MRMDestMem, (ops f32mem:$dst, V4F4:$src),
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"movss {$src, $dst|$dst, $src}">, XS;
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def MOVSDrr : I<0x10, MRMSrcReg, (ops V2F8:$dst, V2F8:$src),
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"movsd {$src, $dst|$dst, $src}">, XD;
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def MOVSDmr : I<0x11, MRMDestMem, (ops f64mem:$dst, RXMM:$src),
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def MOVSDrm : I<0x10, MRMSrcMem, (ops V2F8:$dst, f64mem:$src),
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"movsd {$src, $dst|$dst, $src}">, XD;
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def MOVSDmr : I<0x11, MRMDestMem, (ops f64mem:$dst, V2F8:$src),
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"movsd {$src, $dst|$dst, $src}">, XD;
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def MOVAPSrr: I<0x28, MRMSrcReg, (ops RXMM:$dst, RXMM:$src),
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"movaps {$src, $dst|$dst, $src}">, TB;
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def MOVAPSrm: I<0x28, MRMSrcMem, (ops RXMM:$dst, f32mem:$src),
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"movaps {$src, $dst|$dst, $src}">, TB;
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def MOVAPSmr: I<0x29, MRMDestMem, (ops f32mem:$dst, RXMM:$src),
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"movaps {$src, $dst|$dst, $src}">, TB;
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def MOVAPDrr: I<0x28, MRMSrcReg, (ops RXMM:$dst, RXMM:$src),
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"movapd {$src, $dst|$dst, $src}">, TB, OpSize;
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def MOVAPDrm: I<0x28, MRMSrcMem, (ops RXMM:$dst, f64mem:$src),
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"movapd {$src, $dst|$dst, $src}">, TB, OpSize;
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def MOVAPDmr: I<0x29, MRMDestMem, (ops f64mem:$dst, RXMM:$src),
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"movapd {$src, $dst|$dst, $src}">, TB, OpSize;
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def CVTTSD2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, RXMM:$src),
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def CVTTSD2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, V2F8:$src),
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"cvttsd2si {$src, $dst|$dst, $src}">, XD;
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def CVTTSD2SIrm: I<0x2C, MRMSrcMem, (ops R32:$dst, f64mem:$src),
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"cvttsd2si {$src, $dst|$dst, $src}">, XD;
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def CVTTSS2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, RXMM:$src),
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def CVTTSS2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, V4F4:$src),
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"cvttss2si {$src, $dst|$dst, $src}">, XS;
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def CVTTSS2SIrm: I<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src),
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"cvttss2si {$src, $dst|$dst, $src}">, XS;
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def CVTSD2SSrr: I<0x5A, MRMSrcReg, (ops RXMM:$dst, RXMM:$src),
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def CVTSD2SSrr: I<0x5A, MRMSrcReg, (ops V4F4:$dst, V2F8:$src),
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"cvtsd2ss {$src, $dst|$dst, $src}">, XS;
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def CVTSD2SSrm: I<0x5A, MRMSrcMem, (ops RXMM:$dst, f64mem:$src),
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def CVTSD2SSrm: I<0x5A, MRMSrcMem, (ops V4F4:$dst, f64mem:$src),
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"cvtsd2ss {$src, $dst|$dst, $src}">, XS;
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def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops RXMM:$dst, RXMM:$src),
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def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops V2F8:$dst, V4F4:$src),
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"cvtss2sd {$src, $dst|$dst, $src}">, XD;
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def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops RXMM:$dst, f32mem:$src),
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def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops V2F8:$dst, f32mem:$src),
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"cvtss2sd {$src, $dst|$dst, $src}">, XD;
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def CVTSI2SSrr: I<0x2A, MRMSrcReg, (ops R32:$dst, RXMM:$src),
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def CVTSI2SSrr: I<0x2A, MRMSrcReg, (ops V4F4:$dst, R32:$src),
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"cvtsi2ss {$src, $dst|$dst, $src}">, XS;
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def CVTSI2SSrm: I<0x2A, MRMSrcMem, (ops R32:$dst, f32mem:$src),
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def CVTSI2SSrm: I<0x2A, MRMSrcMem, (ops V4F4:$dst, i32mem:$src),
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"cvtsi2ss {$src, $dst|$dst, $src}">, XS;
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def CVTSI2SDrr: I<0x2A, MRMSrcReg, (ops R32:$dst, RXMM:$src),
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def CVTSI2SDrr: I<0x2A, MRMSrcReg, (ops V2F8:$dst, R32:$src),
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"cvtsi2sd {$src, $dst|$dst, $src}">, XD;
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def CVTSI2SDrm: I<0x2A, MRMSrcMem, (ops R32:$dst, f64mem:$src),
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def CVTSI2SDrm: I<0x2A, MRMSrcMem, (ops V2F8:$dst, i32mem:$src),
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"cvtsi2sd {$src, $dst|$dst, $src}">, XD;
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def SQRTSSrm : I<0x51, MRMSrcMem, (ops RXMM:$dst, f32mem:$src),
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def SQRTSSrm : I<0x51, MRMSrcMem, (ops V4F4:$dst, f32mem:$src),
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"subss {$src, $dst|$dst, $src}">, XS;
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def SQRTSSrr : I<0x51, MRMSrcReg, (ops RXMM:$dst, RXMM:$src),
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def SQRTSSrr : I<0x51, MRMSrcReg, (ops V4F4:$dst, V4F4:$src),
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"subss {$src, $dst|$dst, $src}">, XS;
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def SQRTSDrm : I<0x51, MRMSrcMem, (ops RXMM:$dst, f64mem:$src),
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def SQRTSDrm : I<0x51, MRMSrcMem, (ops V2F8:$dst, f64mem:$src),
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"subsd {$src, $dst|$dst, $src}">, XD;
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def SQRTSDrr : I<0x51, MRMSrcReg, (ops RXMM:$dst, RXMM:$src),
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def SQRTSDrr : I<0x51, MRMSrcReg, (ops V2F8:$dst, V2F8:$src),
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"subsd {$src, $dst|$dst, $src}">, XD;
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def UCOMISDrr: I<0x2E, MRMSrcReg, (ops RXMM:$dst, RXMM:$src),
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def UCOMISDrr: I<0x2E, MRMSrcReg, (ops V2F8:$dst, V2F8:$src),
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"ucomisd {$src, $dst|$dst, $src}">, TB, OpSize;
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def UCOMISDrm: I<0x2E, MRMSrcMem, (ops RXMM:$dst, f64mem:$src),
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def UCOMISDrm: I<0x2E, MRMSrcMem, (ops V2F8:$dst, f64mem:$src),
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"ucomisd {$src, $dst|$dst, $src}">, TB, OpSize;
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def UCOMISSrr: I<0x2E, MRMSrcReg, (ops RXMM:$dst, RXMM:$src),
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def UCOMISSrr: I<0x2E, MRMSrcReg, (ops V4F4:$dst, V4F4:$src),
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"ucomiss {$src, $dst|$dst, $src}">, TB;
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def UCOMISSrm: I<0x2E, MRMSrcMem, (ops RXMM:$dst, f32mem:$src),
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def UCOMISSrm: I<0x2E, MRMSrcMem, (ops V4F4:$dst, f32mem:$src),
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"ucomiss {$src, $dst|$dst, $src}">, TB;
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// Pseudo-instructions that map to fld0 to xorps/xorpd for sse.
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// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
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def FLD0SS : I<0x57, MRMSrcReg, (ops RXMM:$dst),
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def FLD0SS : I<0x57, MRMSrcReg, (ops V4F4:$dst),
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"xorps $dst, $dst">, TB;
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def FLD0SD : I<0x57, MRMSrcReg, (ops RXMM:$dst),
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def FLD0SD : I<0x57, MRMSrcReg, (ops V2F8:$dst),
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"xorpd $dst, $dst">, TB, OpSize;
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let isTwoAddress = 1 in {
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let isCommutable = 1 in {
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def ADDSSrr : I<0x58, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
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def ADDSSrr : I<0x58, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src),
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"addss {$src, $dst|$dst, $src}">, XS;
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def ADDSDrr : I<0x58, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
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def ADDSDrr : I<0x58, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src),
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"addsd {$src, $dst|$dst, $src}">, XD;
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def ANDPSrr : I<0x54, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
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def ANDPSrr : I<0x54, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src),
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"andps {$src, $dst|$dst, $src}">, TB;
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def ANDPDrr : I<0x54, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
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def ANDPDrr : I<0x54, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src),
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"andpd {$src, $dst|$dst, $src}">, TB, OpSize;
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def MULSSrr : I<0x59, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
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def MULSSrr : I<0x59, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src),
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"mulss {$src, $dst|$dst, $src}">, XS;
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def MULSDrr : I<0x59, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
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def MULSDrr : I<0x59, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src),
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"mulsd {$src, $dst|$dst, $src}">, XD;
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def ORPSrr : I<0x56, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
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def ORPSrr : I<0x56, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src),
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"orps {$src, $dst|$dst, $src}">, TB;
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def ORPDrr : I<0x56, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
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def ORPDrr : I<0x56, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src),
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"orpd {$src, $dst|$dst, $src}">, TB, OpSize;
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def XORPSrr : I<0x57, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
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def XORPSrr : I<0x57, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src),
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"xorps {$src, $dst|$dst, $src}">, TB;
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def XORPDrr : I<0x57, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
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def XORPDrr : I<0x57, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src),
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"xorpd {$src, $dst|$dst, $src}">, TB, OpSize;
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}
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def ANDNPSrr : I<0x55, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
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def ANDNPSrr : I<0x55, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src),
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"andnps {$src, $dst|$dst, $src}">, TB;
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def ANDNPDrr : I<0x55, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
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def ANDNPDrr : I<0x55, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src),
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"andnpd {$src, $dst|$dst, $src}">, TB, OpSize;
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def ADDSSrm : I<0x58, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f32mem:$src),
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def ADDSSrm : I<0x58, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src),
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"addss {$src, $dst|$dst, $src}">, XS;
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def ADDSDrm : I<0x58, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f64mem:$src),
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def ADDSDrm : I<0x58, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src),
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"addsd {$src, $dst|$dst, $src}">, XD;
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def MULSSrm : I<0x59, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f32mem:$src),
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def MULSSrm : I<0x59, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src),
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"mulss {$src, $dst|$dst, $src}">, XS;
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def MULSDrm : I<0x59, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f64mem:$src),
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def MULSDrm : I<0x59, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src),
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"mulsd {$src, $dst|$dst, $src}">, XD;
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def DIVSSrm : I<0x5E, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f32mem:$src),
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def DIVSSrm : I<0x5E, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src),
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"divss {$src, $dst|$dst, $src}">, XS;
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def DIVSSrr : I<0x5E, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
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def DIVSSrr : I<0x5E, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src),
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"divss {$src, $dst|$dst, $src}">, XS;
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def DIVSDrm : I<0x5E, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f64mem:$src),
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def DIVSDrm : I<0x5E, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src),
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"divsd {$src, $dst|$dst, $src}">, XD;
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def DIVSDrr : I<0x5E, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
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def DIVSDrr : I<0x5E, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src),
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"divsd {$src, $dst|$dst, $src}">, XD;
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def SUBSSrm : I<0x5C, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f32mem:$src),
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def SUBSSrm : I<0x5C, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src),
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"subss {$src, $dst|$dst, $src}">, XS;
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def SUBSSrr : I<0x5C, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
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def SUBSSrr : I<0x5C, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src),
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"subss {$src, $dst|$dst, $src}">, XS;
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def SUBSDrm : I<0x5C, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f64mem:$src),
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def SUBSDrm : I<0x5C, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src),
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"subsd {$src, $dst|$dst, $src}">, XD;
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def SUBSDrr : I<0x5C, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
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def SUBSDrr : I<0x5C, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src),
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"subsd {$src, $dst|$dst, $src}">, XD;
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def CMPSSrr : I<0xC2, MRMSrcReg,
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(ops RXMM:$dst, RXMM:$src1, RXMM:$src, SSECC:$cc),
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(ops V4F4:$dst, V4F4:$src1, V4F4:$src, SSECC:$cc),
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"cmp${cc}ss {$src, $dst|$dst, $src}">, XS;
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def CMPSSrm : I<0xC2, MRMSrcMem,
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(ops RXMM:$dst, RXMM:$src1, f32mem:$src, SSECC:$cc),
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(ops V4F4:$dst, V4F4:$src1, f32mem:$src, SSECC:$cc),
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"cmp${cc}ss {$src, $dst|$dst, $src}">, XS;
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def CMPSDrr : I<0xC2, MRMSrcReg,
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(ops RXMM:$dst, RXMM:$src1, RXMM:$src, SSECC:$cc),
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(ops V2F8:$dst, V2F8:$src1, V2F8:$src, SSECC:$cc),
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"cmp${cc}sd {$src, $dst|$dst, $src}">, XD;
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def CMPSDrm : I<0xC2, MRMSrcMem,
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(ops RXMM:$dst, RXMM:$src1, f64mem:$src, SSECC:$cc),
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(ops V2F8:$dst, V2F8:$src1, f64mem:$src, SSECC:$cc),
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"cmp${cc}sd {$src, $dst|$dst, $src}">, XD;
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}
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@ -57,7 +57,9 @@ void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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Opc = X86::MOV16mr;
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} else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
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Opc = X86::FST64m;
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} else if (RC == &X86::RXMMRegClass) {
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} else if (RC == &X86::V4F4RegClass) {
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Opc = X86::MOVSSmr;
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} else if (RC == &X86::V2F8RegClass) {
|
||||
Opc = X86::MOVSDmr;
|
||||
} else {
|
||||
assert(0 && "Unknown regclass");
|
||||
@ -79,7 +81,9 @@ void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||
Opc = X86::MOV16rm;
|
||||
} else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
|
||||
Opc = X86::FLD64m;
|
||||
} else if (RC == &X86::RXMMRegClass) {
|
||||
} else if (RC == &X86::V4F4RegClass) {
|
||||
Opc = X86::MOVSSrm;
|
||||
} else if (RC == &X86::V2F8RegClass) {
|
||||
Opc = X86::MOVSDrm;
|
||||
} else {
|
||||
assert(0 && "Unknown regclass");
|
||||
@ -101,8 +105,10 @@ void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
|
||||
Opc = X86::MOV16rr;
|
||||
} else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
|
||||
Opc = X86::FpMOV;
|
||||
} else if (RC == &X86::RXMMRegClass) {
|
||||
Opc = X86::MOVAPDrr;
|
||||
} else if (RC == &X86::V4F4RegClass) {
|
||||
Opc = X86::MOVSSrr;
|
||||
} else if (RC == &X86::V2F8RegClass) {
|
||||
Opc = X86::MOVSDrr;
|
||||
} else {
|
||||
assert(0 && "Unknown regclass");
|
||||
abort();
|
||||
@ -119,7 +125,7 @@ unsigned X86RegisterInfo::isLoadFromStackSlot(MachineInstr *MI,
|
||||
case X86::MOV32rm:
|
||||
case X86::FLD64m:
|
||||
case X86::FLD80m:
|
||||
case X86::MOVAPDrm:
|
||||
case X86::MOVSSrm:
|
||||
case X86::MOVSDrm:
|
||||
if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
|
||||
MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
|
||||
|
@ -104,10 +104,11 @@ def R32 : RegisterClass<"X86", i32, 32, [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]
|
||||
}];
|
||||
}
|
||||
|
||||
// FIXME: These registers can contain both integer and fp values. We should
|
||||
// figure out the right way to deal with that. For now, since they'll be used
|
||||
// for scalar FP, they are being declared f64
|
||||
def RXMM : RegisterClass<"X86", f64, 32,
|
||||
// V4F4, the 4 x f32 class, and V2F8, the 2 x f64 class, which we will use for
|
||||
// Scalar SSE2 floating point support.
|
||||
def V4F4 : RegisterClass<"X86", f32, 32,
|
||||
[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
|
||||
def V2F8 : RegisterClass<"X86", f64, 64,
|
||||
[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
|
||||
|
||||
// FIXME: This sets up the floating point register files as though they are f64
|
||||
|
Loading…
Reference in New Issue
Block a user