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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195711 91177308-0d34-0410-b5e6-96231b3b80d8
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Andrew Trick 2013-11-26 02:03:20 +00:00
parent 59ac92ab4b
commit 151ed66489
1 changed files with 5 additions and 5 deletions
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10
lib/Target/X86/X86ISelLowering.cpp
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@ -17943,12 +17943,12 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
MachineFunction &MF = DAG.getMachineFunction();
bool OptForSize = MF.getFunction()->getAttributes().
hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
// SHLD/SHRD instructions have lower register pressure, but on some
// platforms they have higher latency than the equivalent
// series of shifts/or that would otherwise be generated.
// SHLD/SHRD instructions have lower register pressure, but on some
// platforms they have higher latency than the equivalent
// series of shifts/or that would otherwise be generated.
// Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
// have higer latencies and we are not optimizing for size.
// have higher latencies and we are not optimizing for size.
if (!OptForSize && Subtarget->isSHLDSlow())
return SDValue();