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AVX-512: Added FMA instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189326 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky
parent
47c7eee533
commit
1567abe74f
@ -9132,7 +9132,7 @@ SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
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MachinePointerInfo::getConstantPool(),
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false, false, false, Alignment);
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if (VT.isVector()) {
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MVT XORVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
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MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
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return DAG.getNode(ISD::BITCAST, dl, VT,
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DAG.getNode(ISD::XOR, dl, XORVT,
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DAG.getNode(ISD::BITCAST, dl, XORVT,
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@ -1994,6 +1994,203 @@ def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
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// MOVHLPS patterns
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def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
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(VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
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//===----------------------------------------------------------------------===//
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// FMA - Fused Multiply Operations
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//
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let Constraints = "$src1 = $dst" in {
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multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
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RegisterClass RC, X86MemOperand x86memop,
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PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
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string BrdcstStr, SDNode OpNode, ValueType OpVT> {
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def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, RC:$src3),
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!strconcat(OpcodeStr,"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
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let mayLoad = 1 in
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def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, x86memop:$src3),
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!strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
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(mem_frag addr:$src3))))]>;
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def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
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!strconcat(OpcodeStr, "\t{${src3}", BrdcstStr,
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", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
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[(set RC:$dst, (OpNode RC:$src1, RC:$src2,
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(OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
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}
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} // Constraints = "$src1 = $dst"
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let ExeDomain = SSEPackedSingle in {
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defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}",
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X86Fmadd, v16f32>, EVEX_V512,
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EVEX_CD8<32, CD8VF>;
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defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}",
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X86Fmsub, v16f32>, EVEX_V512,
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EVEX_CD8<32, CD8VF>;
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defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}",
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X86Fmaddsub, v16f32>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}",
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X86Fmsubadd, v16f32>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}",
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X86Fnmadd, v16f32>, EVEX_V512,
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EVEX_CD8<32, CD8VF>;
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defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}",
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X86Fnmsub, v16f32>, EVEX_V512,
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EVEX_CD8<32, CD8VF>;
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}
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let ExeDomain = SSEPackedDouble in {
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defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}",
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X86Fmadd, v8f64>, EVEX_V512,
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VEX_W, EVEX_CD8<64, CD8VF>;
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defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}",
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X86Fmsub, v8f64>, EVEX_V512, VEX_W,
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EVEX_CD8<64, CD8VF>;
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defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}",
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X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
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EVEX_CD8<64, CD8VF>;
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defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}",
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X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
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EVEX_CD8<64, CD8VF>;
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defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}",
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X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
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EVEX_CD8<64, CD8VF>;
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defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}",
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X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
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EVEX_CD8<64, CD8VF>;
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}
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let Constraints = "$src1 = $dst" in {
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multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
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RegisterClass RC, X86MemOperand x86memop,
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PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
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string BrdcstStr, SDNode OpNode, ValueType OpVT> {
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let mayLoad = 1 in
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def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, RC:$src3, x86memop:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
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[(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
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def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
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!strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
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", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
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[(set RC:$dst, (OpNode RC:$src1,
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(OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
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}
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} // Constraints = "$src1 = $dst"
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let ExeDomain = SSEPackedSingle in {
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defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}",
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X86Fmadd, v16f32>, EVEX_V512,
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EVEX_CD8<32, CD8VF>;
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defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}",
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X86Fmsub, v16f32>, EVEX_V512,
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EVEX_CD8<32, CD8VF>;
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defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}",
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X86Fmaddsub, v16f32>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}",
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X86Fmsubadd, v16f32>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}",
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X86Fnmadd, v16f32>, EVEX_V512,
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EVEX_CD8<32, CD8VF>;
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defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}",
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X86Fnmsub, v16f32>, EVEX_V512,
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EVEX_CD8<32, CD8VF>;
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}
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let ExeDomain = SSEPackedDouble in {
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defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}",
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X86Fmadd, v8f64>, EVEX_V512,
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VEX_W, EVEX_CD8<64, CD8VF>;
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defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}",
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X86Fmsub, v8f64>, EVEX_V512, VEX_W,
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EVEX_CD8<64, CD8VF>;
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defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}",
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X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
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EVEX_CD8<64, CD8VF>;
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defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}",
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X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
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EVEX_CD8<64, CD8VF>;
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defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}",
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X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
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EVEX_CD8<64, CD8VF>;
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defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}",
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X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
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EVEX_CD8<64, CD8VF>;
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}
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// Scalar FMA
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let Constraints = "$src1 = $dst" in {
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multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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RegisterClass RC, ValueType OpVT,
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X86MemOperand x86memop, Operand memop,
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PatFrag mem_frag> {
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let isCommutable = 1 in
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def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set RC:$dst,
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(OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
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let mayLoad = 1 in
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def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, f128mem:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set RC:$dst,
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(OpVT (OpNode RC:$src2, RC:$src1,
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(mem_frag addr:$src3))))]>;
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}
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} // Constraints = "$src1 = $dst"
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defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss{z}", X86Fmadd, FR32X,
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f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
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defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd{z}", X86Fmadd, FR64X,
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f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
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defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss{z}", X86Fmsub, FR32X,
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f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
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defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd{z}", X86Fmsub, FR64X,
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f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
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defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss{z}", X86Fnmadd, FR32X,
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f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
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defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd{z}", X86Fnmadd, FR64X,
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f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
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defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss{z}", X86Fnmsub, FR32X,
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f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
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defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd{z}", X86Fnmsub, FR64X,
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f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
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//===----------------------------------------------------------------------===//
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// VSHUFPS - VSHUFPD Operations
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83
test/CodeGen/X86/avx512-fma.ll
Normal file
83
test/CodeGen/X86/avx512-fma.ll
Normal file
@ -0,0 +1,83 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -fp-contract=fast | FileCheck %s
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; CHECK-LABEL: test_x86_fmadd_ps_z
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; CHECK: vfmadd213ps %zmm2, %zmm1, %zmm0
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; CHECK: ret
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define <16 x float> @test_x86_fmadd_ps_z(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
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%x = fmul <16 x float> %a0, %a1
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%res = fadd <16 x float> %x, %a2
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ret <16 x float> %res
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}
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; CHECK-LABEL: test_x86_fmsub_ps_z
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; CHECK: vfmsub213ps %zmm2, %zmm1, %zmm0
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; CHECK: ret
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define <16 x float> @test_x86_fmsub_ps_z(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
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%x = fmul <16 x float> %a0, %a1
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%res = fsub <16 x float> %x, %a2
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ret <16 x float> %res
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}
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; CHECK-LABEL: test_x86_fnmadd_ps_z
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; CHECK: vfnmadd213ps %zmm2, %zmm1, %zmm0
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; CHECK: ret
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define <16 x float> @test_x86_fnmadd_ps_z(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
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%x = fmul <16 x float> %a0, %a1
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%res = fsub <16 x float> %a2, %x
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ret <16 x float> %res
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}
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; CHECK-LABEL: test_x86_fnmsub_ps_z
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; CHECK: vfnmsub213ps %zmm2, %zmm1, %zmm0
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; CHECK: ret
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define <16 x float> @test_x86_fnmsub_ps_z(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
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%x = fmul <16 x float> %a0, %a1
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%y = fsub <16 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00,
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float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00,
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float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00,
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float -0.000000e+00>, %x
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%res = fsub <16 x float> %y, %a2
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ret <16 x float> %res
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}
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; CHECK-LABEL: test_x86_fmadd_pd_z
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; CHECK: vfmadd213pd %zmm2, %zmm1, %zmm0
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; CHECK: ret
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define <8 x double> @test_x86_fmadd_pd_z(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
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%x = fmul <8 x double> %a0, %a1
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%res = fadd <8 x double> %x, %a2
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ret <8 x double> %res
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}
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; CHECK-LABEL: test_x86_fmsub_pd_z
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; CHECK: vfmsub213pd %zmm2, %zmm1, %zmm0
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; CHECK: ret
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define <8 x double> @test_x86_fmsub_pd_z(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
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%x = fmul <8 x double> %a0, %a1
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%res = fsub <8 x double> %x, %a2
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ret <8 x double> %res
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}
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define double @test_x86_fmsub_sd_z(double %a0, double %a1, double %a2) {
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%x = fmul double %a0, %a1
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%res = fsub double %x, %a2
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ret double %res
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}
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;CHECK-LABEL: test132_br
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;CHECK: vfmadd132ps LCP{{.*}}(%rip){1to16}
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;CHECK: ret
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define <16 x float> @test132_br(<16 x float> %a1, <16 x float> %a2) nounwind {
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%b1 = fmul <16 x float> %a1, <float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000>
|
||||
%b2 = fadd <16 x float> %b1, %a2
|
||||
ret <16 x float> %b2
|
||||
}
|
||||
|
||||
;CHECK-LABEL: test213_br
|
||||
;CHECK: vfmadd213ps LCP{{.*}}(%rip){1to16}
|
||||
;CHECK: ret
|
||||
define <16 x float> @test213_br(<16 x float> %a1, <16 x float> %a2) nounwind {
|
||||
%b1 = fmul <16 x float> %a1, %a2
|
||||
%b2 = fadd <16 x float> %b1, <float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000>
|
||||
ret <16 x float> %b2
|
||||
}
|
||||
Loading…
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Reference in New Issue
Block a user