6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-08-05 13:26:55 +00:00
Code Issues Projects Releases Wiki Activity

Revert 69952. Causes testsuite failures on linux x86-64.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69967 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola
2009-04-24 12:40:33 +00:00
parent f6b9f260ed
commit 15684b2955
25 changed files with 2187 additions and 1640 deletions
Download Patch File Download Diff File Expand all files Collapse all files

181
lib/Target/PowerPC/PPCInstrAltivec.td
View File

@@ -15,118 +15,96 @@
// Altivec transformation functions and pattern fragments.
//
/// VPKUHUM_shuffle_mask/VPKUWUM_shuffle_mask - Return true if this is a valid
/// shuffle mask for the VPKUHUM or VPKUWUM instructions.
def VPKUHUM_shuffle_mask : PatLeaf<(build_vector), [{
return PPC::isVPKUHUMShuffleMask(N, false);
}]>;
def VPKUWUM_shuffle_mask : PatLeaf<(build_vector), [{
return PPC::isVPKUWUMShuffleMask(N, false);
}]>;
def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
(vector_shuffle node:$lhs, node:$rhs), [{
return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), false);
def VPKUHUM_unary_shuffle_mask : PatLeaf<(build_vector), [{
return PPC::isVPKUHUMShuffleMask(N, true);
}]>;
def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
(vector_shuffle node:$lhs, node:$rhs), [{
return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), false);
}]>;
def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
(vector_shuffle node:$lhs, node:$rhs), [{
return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), true);
}]>;
def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
(vector_shuffle node:$lhs, node:$rhs), [{
return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), true);
def VPKUWUM_unary_shuffle_mask : PatLeaf<(build_vector), [{
return PPC::isVPKUWUMShuffleMask(N, true);
}]>;
def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
(vector_shuffle node:$lhs, node:$rhs), [{
return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false);
def VMRGLB_shuffle_mask : PatLeaf<(build_vector), [{
return PPC::isVMRGLShuffleMask(N, 1, false);
}]>;
def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
(vector_shuffle node:$lhs, node:$rhs), [{
return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false);
def VMRGLH_shuffle_mask : PatLeaf<(build_vector), [{
return PPC::isVMRGLShuffleMask(N, 2, false);
}]>;
def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
(vector_shuffle node:$lhs, node:$rhs), [{
return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false);
def VMRGLW_shuffle_mask : PatLeaf<(build_vector), [{
return PPC::isVMRGLShuffleMask(N, 4, false);
}]>;
def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
(vector_shuffle node:$lhs, node:$rhs), [{
return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false);
def VMRGHB_shuffle_mask : PatLeaf<(build_vector), [{
return PPC::isVMRGHShuffleMask(N, 1, false);
}]>;
def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
(vector_shuffle node:$lhs, node:$rhs), [{
return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false);
def VMRGHH_shuffle_mask : PatLeaf<(build_vector), [{
return PPC::isVMRGHShuffleMask(N, 2, false);
}]>;
def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
(vector_shuffle node:$lhs, node:$rhs), [{
return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false);
def VMRGHW_shuffle_mask : PatLeaf<(build_vector), [{
return PPC::isVMRGHShuffleMask(N, 4, false);
}]>;
def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
(vector_shuffle node:$lhs, node:$rhs), [{
return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true);
def VMRGLB_unary_shuffle_mask : PatLeaf<(build_vector), [{
return PPC::isVMRGLShuffleMask(N, 1, true);
}]>;
def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
(vector_shuffle node:$lhs, node:$rhs), [{
return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true);
def VMRGLH_unary_shuffle_mask : PatLeaf<(build_vector), [{
return PPC::isVMRGLShuffleMask(N, 2, true);
}]>;
def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
(vector_shuffle node:$lhs, node:$rhs), [{
return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true);
def VMRGLW_unary_shuffle_mask : PatLeaf<(build_vector), [{
return PPC::isVMRGLShuffleMask(N, 4, true);
}]>;
def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
(vector_shuffle node:$lhs, node:$rhs), [{
return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true);
def VMRGHB_unary_shuffle_mask : PatLeaf<(build_vector), [{
return PPC::isVMRGHShuffleMask(N, 1, true);
}]>;
def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
(vector_shuffle node:$lhs, node:$rhs), [{
return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true);
def VMRGHH_unary_shuffle_mask : PatLeaf<(build_vector), [{
return PPC::isVMRGHShuffleMask(N, 2, true);
}]>;
def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
(vector_shuffle node:$lhs, node:$rhs), [{
return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true);
def VMRGHW_unary_shuffle_mask : PatLeaf<(build_vector), [{
return PPC::isVMRGHShuffleMask(N, 4, true);
}]>;
def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{
def VSLDOI_get_imm : SDNodeXForm<build_vector, [{
return getI32Imm(PPC::isVSLDOIShuffleMask(N, false));
}]>;
def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
(vector_shuffle node:$lhs, node:$rhs), [{
def VSLDOI_shuffle_mask : PatLeaf<(build_vector), [{
return PPC::isVSLDOIShuffleMask(N, false) != -1;
}], VSLDOI_get_imm>;
/// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into
/// vector_shuffle(X,undef,mask) by the dag combiner.
def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{
def VSLDOI_unary_get_imm : SDNodeXForm<build_vector, [{
return getI32Imm(PPC::isVSLDOIShuffleMask(N, true));
}]>;
def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
(vector_shuffle node:$lhs, node:$rhs), [{
def VSLDOI_unary_shuffle_mask : PatLeaf<(build_vector), [{
return PPC::isVSLDOIShuffleMask(N, true) != -1;
}], VSLDOI_unary_get_imm>;
// VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{
def VSPLTB_get_imm : SDNodeXForm<build_vector, [{
return getI32Imm(PPC::getVSPLTImmediate(N, 1));
}]>;
def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
(vector_shuffle node:$lhs, node:$rhs), [{
return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1);
def VSPLTB_shuffle_mask : PatLeaf<(build_vector), [{
return PPC::isSplatShuffleMask(N, 1);
}], VSPLTB_get_imm>;
def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{
def VSPLTH_get_imm : SDNodeXForm<build_vector, [{
return getI32Imm(PPC::getVSPLTImmediate(N, 2));
}]>;
def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
(vector_shuffle node:$lhs, node:$rhs), [{
return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2);
def VSPLTH_shuffle_mask : PatLeaf<(build_vector), [{
return PPC::isSplatShuffleMask(N, 2);
}], VSPLTH_get_imm>;
def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{
def VSPLTW_get_imm : SDNodeXForm<build_vector, [{
return getI32Imm(PPC::getVSPLTImmediate(N, 4));
}]>;
def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
(vector_shuffle node:$lhs, node:$rhs), [{
return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4);
def VSPLTW_shuffle_mask : PatLeaf<(build_vector), [{
return PPC::isSplatShuffleMask(N, 4);
}], VSPLTW_get_imm>;
@@ -290,7 +268,8 @@ def VSEL : VA1a_Int<42, "vsel", int_ppc_altivec_vsel>;
def VSLDOI : VAForm_2<44, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, u5imm:$SH),
"vsldoi $vD, $vA, $vB, $SH", VecFP,
[(set VRRC:$vD,
(vsldoi_shuffle:$SH (v16i8 VRRC:$vA), VRRC:$vB))]>;
(vector_shuffle (v16i8 VRRC:$vA), VRRC:$vB,
VSLDOI_shuffle_mask:$SH))]>;
// VX-Form instructions. AltiVec arithmetic ops.
def VADDFP : VXForm_1<10, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
@@ -366,22 +345,28 @@ def VMINUW : VX1_Int< 642, "vminuw", int_ppc_altivec_vminuw>;
def VMRGHB : VXForm_1< 12, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
"vmrghb $vD, $vA, $vB", VecFP,
[(set VRRC:$vD, (vmrghb_shuffle VRRC:$vA, VRRC:$vB))]>;
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
VRRC:$vB, VMRGHB_shuffle_mask))]>;
def VMRGHH : VXForm_1< 76, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
"vmrghh $vD, $vA, $vB", VecFP,
[(set VRRC:$vD, (vmrghh_shuffle VRRC:$vA, VRRC:$vB))]>;
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
VRRC:$vB, VMRGHH_shuffle_mask))]>;
def VMRGHW : VXForm_1<140, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
"vmrghw $vD, $vA, $vB", VecFP,
[(set VRRC:$vD, (vmrghw_shuffle VRRC:$vA, VRRC:$vB))]>;
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
VRRC:$vB, VMRGHW_shuffle_mask))]>;
def VMRGLB : VXForm_1<268, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
"vmrglb $vD, $vA, $vB", VecFP,
[(set VRRC:$vD, (vmrglb_shuffle VRRC:$vA, VRRC:$vB))]>;
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
VRRC:$vB, VMRGLB_shuffle_mask))]>;
def VMRGLH : VXForm_1<332, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
"vmrglh $vD, $vA, $vB", VecFP,
[(set VRRC:$vD, (vmrglh_shuffle VRRC:$vA, VRRC:$vB))]>;
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
VRRC:$vB, VMRGLH_shuffle_mask))]>;
def VMRGLW : VXForm_1<396, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
"vmrglw $vD, $vA, $vB", VecFP,
[(set VRRC:$vD, (vmrglw_shuffle VRRC:$vA, VRRC:$vB))]>;
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
VRRC:$vB, VMRGLW_shuffle_mask))]>;
def VMSUMMBM : VA1a_Int<37, "vmsummbm", int_ppc_altivec_vmsummbm>;
def VMSUMSHM : VA1a_Int<40, "vmsumshm", int_ppc_altivec_vmsumshm>;
@@ -455,16 +440,16 @@ def VSLW : VX1_Int< 388, "vslw", int_ppc_altivec_vslw>;
def VSPLTB : VXForm_1<524, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
"vspltb $vD, $vB, $UIMM", VecPerm,
[(set VRRC:$vD,
(vspltb_shuffle:$UIMM (v16i8 VRRC:$vB), (undef)))]>;
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
VSPLTB_shuffle_mask:$UIMM))]>;
def VSPLTH : VXForm_1<588, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
"vsplth $vD, $vB, $UIMM", VecPerm,
[(set VRRC:$vD,
(vsplth_shuffle:$UIMM (v16i8 VRRC:$vB), (undef)))]>;
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
VSPLTH_shuffle_mask:$UIMM))]>;
def VSPLTW : VXForm_1<652, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
"vspltw $vD, $vB, $UIMM", VecPerm,
[(set VRRC:$vD,
(vspltw_shuffle:$UIMM (v16i8 VRRC:$vB), (undef)))]>;
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
VSPLTW_shuffle_mask:$UIMM))]>;
def VSR : VX1_Int< 708, "vsr" , int_ppc_altivec_vsr>;
def VSRO : VX1_Int<1100, "vsro" , int_ppc_altivec_vsro>;
@@ -494,13 +479,13 @@ def VPKSWSS : VX1_Int<462, "vpkswss", int_ppc_altivec_vpkswss>;
def VPKSWUS : VX1_Int<334, "vpkswus", int_ppc_altivec_vpkswus>;
def VPKUHUM : VXForm_1<14, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
"vpkuhum $vD, $vA, $vB", VecFP,
[(set VRRC:$vD,
(vpkuhum_shuffle (v16i8 VRRC:$vA), VRRC:$vB))]>;
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
VRRC:$vB, VPKUHUM_shuffle_mask))]>;
def VPKUHUS : VX1_Int<142, "vpkuhus", int_ppc_altivec_vpkuhus>;
def VPKUWUM : VXForm_1<78, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
"vpkuwum $vD, $vA, $vB", VecFP,
[(set VRRC:$vD,
(vpkuwum_shuffle (v16i8 VRRC:$vA), VRRC:$vB))]>;
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
VRRC:$vB, VPKUWUM_shuffle_mask))]>;
def VPKUWUS : VX1_Int<206, "vpkuwus", int_ppc_altivec_vpkuwus>;
// Vector Unpack.
@@ -618,25 +603,25 @@ def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
// Shuffles.
// Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x)
def:Pat<(vsldoi_unary_shuffle:$in (v16i8 VRRC:$vA), undef),
(VSLDOI VRRC:$vA, VRRC:$vA, (VSLDOI_unary_get_imm VRRC:$in))>;
def:Pat<(vpkuwum_unary_shuffle (v16i8 VRRC:$vA), undef),
def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VSLDOI_unary_shuffle_mask:$in),
(VSLDOI VRRC:$vA, VRRC:$vA, VSLDOI_unary_shuffle_mask:$in)>;
def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef,VPKUWUM_unary_shuffle_mask:$in),
(VPKUWUM VRRC:$vA, VRRC:$vA)>;
def:Pat<(vpkuhum_unary_shuffle (v16i8 VRRC:$vA), undef),
def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef,VPKUHUM_unary_shuffle_mask:$in),
(VPKUHUM VRRC:$vA, VRRC:$vA)>;
// Match vmrg*(x,x)
def:Pat<(vmrglb_unary_shuffle (v16i8 VRRC:$vA), undef),
def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLB_unary_shuffle_mask:$in),
(VMRGLB VRRC:$vA, VRRC:$vA)>;
def:Pat<(vmrglh_unary_shuffle (v16i8 VRRC:$vA), undef),
def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLH_unary_shuffle_mask:$in),
(VMRGLH VRRC:$vA, VRRC:$vA)>;
def:Pat<(vmrglw_unary_shuffle (v16i8 VRRC:$vA), undef),
def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLW_unary_shuffle_mask:$in),
(VMRGLW VRRC:$vA, VRRC:$vA)>;
def:Pat<(vmrghb_unary_shuffle (v16i8 VRRC:$vA), undef),
def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHB_unary_shuffle_mask:$in),
(VMRGHB VRRC:$vA, VRRC:$vA)>;
def:Pat<(vmrghh_unary_shuffle (v16i8 VRRC:$vA), undef),
def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHH_unary_shuffle_mask:$in),
(VMRGHH VRRC:$vA, VRRC:$vA)>;
def:Pat<(vmrghw_unary_shuffle (v16i8 VRRC:$vA), undef),
def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHW_unary_shuffle_mask:$in),
(VMRGHW VRRC:$vA, VRRC:$vA)>;
// Logical Operations