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[X86][SchedModel] Fixed missing/wrong scheduling model found by code inspection.
Source: Agner Fog's Instruction tables. Related to <rdar://problem/15607571> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215045 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -199,11 +199,11 @@ multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
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def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst),
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(ins DstRC:$src1, SrcRC:$src2), asm,
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[(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
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NoItinerary, d>;
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NoItinerary, d>, Sched<[WriteCvtI2F]>;
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def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst),
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(ins DstRC:$src1, x86memop:$src2), asm,
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[(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
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NoItinerary, d>;
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NoItinerary, d>, Sched<[WriteCvtI2FLd]>;
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}
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//===----------------------------------------------------------------------===//
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@ -1017,7 +1017,7 @@ def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
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// For disassembler
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let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
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SchedRW = [WriteMove] in {
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SchedRW = [WriteFShuffle] in {
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def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
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"movaps\t{$src, $dst|$dst, $src}", [],
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IIC_SSE_MOVA_P_RR>;
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