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Add a big assert making sure 2 address instructions are formed right

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5057 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2002-12-15 21:02:20 +00:00
parent 315bad0bc6
commit 15f96db4d9
1 changed files with 6 additions and 0 deletions
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6
lib/CodeGen/RegAllocSimple.cpp
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@@ -379,6 +379,12 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
if (TM.getInstrInfo().isTwoAddrInstr(MI->getOpcode()) && i == 0) { if (TM.getInstrInfo().isTwoAddrInstr(MI->getOpcode()) && i == 0) {
// must be same register number as the first operand // must be same register number as the first operand
// This maps a = b + c into b += c, and saves b into a's spot // This maps a = b + c into b += c, and saves b into a's spot
assert(MI->getOperand(1).isRegister() &&
MI->getOperand(1).getAllocatedRegNum() &&
MF->getRegClass(virtualReg) ==
PhysRegClasses[MI->getOperand(1).getAllocatedRegNum()] &&
"Two address instruction invalid!");
physReg = MI->getOperand(1).getAllocatedRegNum(); physReg = MI->getOperand(1).getAllocatedRegNum();
} else { } else {
physReg = getFreeReg(virtualReg); physReg = getFreeReg(virtualReg);