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optimize cttz and ctlz when we can prove something about the
leading/trailing bits. Patch by Alastair Lynn! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92706 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3144,7 +3144,40 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
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II->getOperand(1));
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II->getOperand(1));
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}
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}
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break;
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break;
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case Intrinsic::cttz: {
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// If all bits below the first known one are known zero,
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// this value is constant.
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const IntegerType *IT = cast<IntegerType>(II->getOperand(1)->getType());
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uint32_t BitWidth = IT->getBitWidth();
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APInt KnownZero(BitWidth, 0);
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APInt KnownOne(BitWidth, 0);
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ComputeMaskedBits(II->getOperand(1), APInt::getAllOnesValue(BitWidth),
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KnownZero, KnownOne);
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unsigned TrailingZeros = KnownOne.countTrailingZeros();
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APInt Mask(APInt::getLowBitsSet(BitWidth, TrailingZeros));
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if ((Mask & KnownZero) == Mask)
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return ReplaceInstUsesWith(CI, ConstantInt::get(IT,
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APInt(BitWidth, TrailingZeros)));
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}
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break;
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case Intrinsic::ctlz: {
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// If all bits above the first known one are known zero,
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// this value is constant.
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const IntegerType *IT = cast<IntegerType>(II->getOperand(1)->getType());
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uint32_t BitWidth = IT->getBitWidth();
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APInt KnownZero(BitWidth, 0);
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APInt KnownOne(BitWidth, 0);
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ComputeMaskedBits(II->getOperand(1), APInt::getAllOnesValue(BitWidth),
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KnownZero, KnownOne);
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unsigned LeadingZeros = KnownOne.countLeadingZeros();
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APInt Mask(APInt::getHighBitsSet(BitWidth, LeadingZeros));
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if ((Mask & KnownZero) == Mask)
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return ReplaceInstUsesWith(CI, ConstantInt::get(IT,
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APInt(BitWidth, LeadingZeros)));
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}
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break;
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case Intrinsic::uadd_with_overflow: {
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case Intrinsic::uadd_with_overflow: {
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Value *LHS = II->getOperand(1), *RHS = II->getOperand(2);
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Value *LHS = II->getOperand(1), *RHS = II->getOperand(2);
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const IntegerType *IT = cast<IntegerType>(II->getOperand(1)->getType());
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const IntegerType *IT = cast<IntegerType>(II->getOperand(1)->getType());
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@ -5,6 +5,8 @@
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declare %overflow.result @llvm.uadd.with.overflow.i8(i8, i8)
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declare %overflow.result @llvm.uadd.with.overflow.i8(i8, i8)
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declare %overflow.result @llvm.umul.with.overflow.i8(i8, i8)
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declare %overflow.result @llvm.umul.with.overflow.i8(i8, i8)
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declare double @llvm.powi.f64(double, i32) nounwind readonly
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declare double @llvm.powi.f64(double, i32) nounwind readonly
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declare i32 @llvm.cttz.i32(i32) nounwind readnone
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declare i8 @llvm.ctlz.i8(i8) nounwind readnone
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define i8 @test1(i8 %A, i8 %B) {
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define i8 @test1(i8 %A, i8 %B) {
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%x = call %overflow.result @llvm.uadd.with.overflow.i8(i8 %A, i8 %B)
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%x = call %overflow.result @llvm.uadd.with.overflow.i8(i8 %A, i8 %B)
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@ -79,7 +81,6 @@ define i8 @test6(i8 %A, i1* %overflowPtr) {
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; CHECK-NEXT: ret i8 %A
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; CHECK-NEXT: ret i8 %A
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}
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}
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define void @powi(double %V, double *%P) {
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define void @powi(double %V, double *%P) {
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entry:
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entry:
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%A = tail call double @llvm.powi.f64(double %V, i32 -1) nounwind
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%A = tail call double @llvm.powi.f64(double %V, i32 -1) nounwind
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@ -98,4 +99,26 @@ entry:
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; CHECK: volatile store double %V
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; CHECK: volatile store double %V
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}
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}
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define i32 @cttz(i32 %a)
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{
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entry:
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%or = or i32 %a, 8
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%and = and i32 %or, -8
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%count = tail call i32 @llvm.cttz.i32(i32 %and) nounwind readnone
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ret i32 %count
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; CHECK: @cttz
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret i32 3
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}
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define i8 @ctlz(i8 %a)
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{
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entry:
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%or = or i8 %a, 32
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%and = and i8 %or, 63
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%count = tail call i8 @llvm.ctlz.i8(i8 %and) nounwind readnone
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ret i8 %count
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; CHECK: @ctlz
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret i8 2
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}
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