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ARM simplify the postidx_reg operand encoding.

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The immediate portion of the operand is just a boolean (the 'U' bit indicating
add vs. subtract). Treat it as such.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136969 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2011-08-05 16:11:38 +00:00
parent ca8c70b953
commit 16578b5088
4 changed files with 14 additions and 11 deletions
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10
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
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@@ -1543,10 +1543,16 @@ static bool DisassembleLdStMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
++OpIdx;
} else {
// Disassemble the offset reg (Rm).
unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, 0);
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
decodeRm(insn))));
MI.addOperand(MCOperand::CreateImm(Offset));
// FIXME: Remove the 'else' once done w/ addrmode3 refactor.
if (Opcode == ARM::STRHTr || Opcode == ARM::LDRSBTr ||
Opcode == ARM::LDRHTr || Opcode == ARM::LDRSHTr)
MI.addOperand(MCOperand::CreateImm(getUBit(insn)));
else {
unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, 0);
MI.addOperand(MCOperand::CreateImm(Offset));
}
OpIdx += 2;
}