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AVX-512: Added masked SHIFT commands, more encoding tests

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189005 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky
2013-08-22 12:18:28 +00:00
parent 7ddda4704c
commit 1765e74c15
3 changed files with 67 additions and 40 deletions
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3
lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
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@@ -868,11 +868,12 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
case X86II::MRM6r: case X86II::MRM7r: case X86II::MRM6r: case X86II::MRM7r:
// MRM0r-MRM7r instructions forms: // MRM0r-MRM7r instructions forms:
// dst(VEX_4V), src(ModR/M), imm8 // dst(VEX_4V), src(ModR/M), imm8
if (HasVEX_4V) {
VEX_4V = getVEXRegisterEncoding(MI, CurOp); VEX_4V = getVEXRegisterEncoding(MI, CurOp);
if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
EVEX_V2 = 0x0; EVEX_V2 = 0x0;
CurOp++; CurOp++;
}
if (HasEVEX_K) if (HasEVEX_K)
EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++); EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);

56
lib/Target/X86/X86InstrAVX512.td
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@@ -1720,78 +1720,98 @@ defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem, memopv8i
// AVX-512 Shift instructions // AVX-512 Shift instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM, multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
string OpcodeStr, string OpcodeStr, SDNode OpNode, RegisterClass RC,
SDNode OpNode, RegisterClass RC, ValueType vt, ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
X86MemOperand x86memop, PatFrag mem_frag> { RegisterClass KRC> {
def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst), def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
(ins RC:$src1, i32i8imm:$src2), (ins RC:$src1, i32i8imm:$src2),
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[(set RC:$dst, (vt (OpNode RC:$src1, (i32 imm:$src2))))], [(set RC:$dst, (vt (OpNode RC:$src1, (i32 imm:$src2))))],
SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V; SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
(ins KRC:$mask, RC:$src1, i32i8imm:$src2),
!strconcat(OpcodeStr,
"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
[], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst), def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
(ins x86memop:$src1, i32i8imm:$src2), (ins x86memop:$src1, i32i8imm:$src2),
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[(set RC:$dst, (OpNode (mem_frag addr:$src1), [(set RC:$dst, (OpNode (mem_frag addr:$src1),
(i32 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V; (i32 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
(ins KRC:$mask, x86memop:$src1, i32i8imm:$src2),
!strconcat(OpcodeStr,
"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
[], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
} }
multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode, multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
RegisterClass RC, ValueType vt, ValueType SrcVT, RegisterClass RC, ValueType vt, ValueType SrcVT,
PatFrag bc_frag> { PatFrag bc_frag, RegisterClass KRC> {
// src2 is always 128-bit // src2 is always 128-bit
def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst), def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
(ins RC:$src1, VR128X:$src2), (ins RC:$src1, VR128X:$src2),
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))], [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V; SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
(ins KRC:$mask, RC:$src1, VR128X:$src2),
!strconcat(OpcodeStr,
"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
[], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst), def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
(ins RC:$src1, i128mem:$src2), (ins RC:$src1, i128mem:$src2),
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[(set RC:$dst, (vt (OpNode RC:$src1, [(set RC:$dst, (vt (OpNode RC:$src1,
(bc_frag (memopv2i64 addr:$src2)))))], (bc_frag (memopv2i64 addr:$src2)))))],
SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V; SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
(ins KRC:$mask, RC:$src1, i128mem:$src2),
!strconcat(OpcodeStr,
"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
[], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
} }
defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli, defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
VR512, v16i32, i512mem, memopv16i32>, EVEX_V512, VR512, v16i32, i512mem, memopv16i32, VK16WM>,
EVEX_CD8<32, CD8VF>; EVEX_V512, EVEX_CD8<32, CD8VF>;
defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl, defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
VR512, v16i32, v4i32, bc_v4i32>, EVEX_V512, VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
EVEX_CD8<32, CD8VQ>; EVEX_CD8<32, CD8VQ>;
defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli, defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
VR512, v8i64, i512mem, memopv8i64>, EVEX_V512, VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
EVEX_CD8<64, CD8VF>, VEX_W; EVEX_CD8<64, CD8VF>, VEX_W;
defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl, defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
VR512, v8i64, v2i64, bc_v2i64>, EVEX_V512, VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
EVEX_CD8<64, CD8VQ>, VEX_W; EVEX_CD8<64, CD8VQ>, VEX_W;
defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli, defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
VR512, v16i32, i512mem, memopv16i32>, EVEX_V512, VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
EVEX_CD8<32, CD8VF>; EVEX_CD8<32, CD8VF>;
defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl, defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
VR512, v16i32, v4i32, bc_v4i32>, EVEX_V512, VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
EVEX_CD8<32, CD8VQ>; EVEX_CD8<32, CD8VQ>;
defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli, defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
VR512, v8i64, i512mem, memopv8i64>, EVEX_V512, VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
EVEX_CD8<64, CD8VF>, VEX_W; EVEX_CD8<64, CD8VF>, VEX_W;
defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl, defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
VR512, v8i64, v2i64, bc_v2i64>, EVEX_V512, VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
EVEX_CD8<64, CD8VQ>, VEX_W; EVEX_CD8<64, CD8VQ>, VEX_W;
defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai, defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
VR512, v16i32, i512mem, memopv16i32>, EVEX_V512, VR512, v16i32, i512mem, memopv16i32, VK16WM>,
EVEX_CD8<32, CD8VF>; EVEX_V512, EVEX_CD8<32, CD8VF>;
defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra, defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
VR512, v16i32, v4i32, bc_v4i32>, EVEX_V512, VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
EVEX_CD8<32, CD8VQ>; EVEX_CD8<32, CD8VQ>;
defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai, defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
VR512, v8i64, i512mem, memopv8i64>, EVEX_V512, VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
EVEX_CD8<64, CD8VF>, VEX_W; EVEX_CD8<64, CD8VF>, VEX_W;
defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra, defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
VR512, v8i64, v2i64, bc_v2i64>, EVEX_V512, VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
EVEX_CD8<64, CD8VQ>, VEX_W; EVEX_CD8<64, CD8VQ>, VEX_W;
//===-------------------------------------------------------------------===// //===-------------------------------------------------------------------===//

30
utils/TableGen/X86RecognizableInstr.cpp
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@@ -818,17 +818,20 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
case X86Local::MRM5r: case X86Local::MRM5r:
case X86Local::MRM6r: case X86Local::MRM6r:
case X86Local::MRM7r: case X86Local::MRM7r:
{
// Operand 1 is a register operand in the R/M field. // Operand 1 is a register operand in the R/M field.
// Operand 2 (optional) is an immediate or relocation. // Operand 2 (optional) is an immediate or relocation.
// Operand 3 (optional) is an immediate. // Operand 3 (optional) is an immediate.
if (HasVEX_4VPrefix) unsigned kOp = (HasEVEX_K) ? 1:0;
assert(numPhysicalOperands <= 3 && unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
"Unexpected number of operands for MRMnRFrm with VEX_4V"); if (numPhysicalOperands > 3 + kOp + Op4v)
else llvm_unreachable("Unexpected number of operands for MRMnr");
assert(numPhysicalOperands <= 3 && }
"Unexpected number of operands for MRMnRFrm");
if (HasVEX_4VPrefix) if (HasVEX_4VPrefix)
HANDLE_OPERAND(vvvvRegister) HANDLE_OPERAND(vvvvRegister)
if (HasEVEX_K)
HANDLE_OPERAND(writemaskRegister)
HANDLE_OPTIONAL(rmRegister) HANDLE_OPTIONAL(rmRegister)
HANDLE_OPTIONAL(relocation) HANDLE_OPTIONAL(relocation)
HANDLE_OPTIONAL(immediate) HANDLE_OPTIONAL(immediate)
@@ -841,16 +844,19 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
case X86Local::MRM5m: case X86Local::MRM5m:
case X86Local::MRM6m: case X86Local::MRM6m:
case X86Local::MRM7m: case X86Local::MRM7m:
{
// Operand 1 is a memory operand (possibly SIB-extended) // Operand 1 is a memory operand (possibly SIB-extended)
// Operand 2 (optional) is an immediate or relocation. // Operand 2 (optional) is an immediate or relocation.
if (HasVEX_4VPrefix) unsigned kOp = (HasEVEX_K) ? 1:0;
assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
"Unexpected number of operands for MRMnMFrm"); if (numPhysicalOperands < 1 + kOp + Op4v ||
else numPhysicalOperands > 2 + kOp + Op4v)
assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && llvm_unreachable("Unexpected number of operands for MRMnm");
"Unexpected number of operands for MRMnMFrm"); }
if (HasVEX_4VPrefix) if (HasVEX_4VPrefix)
HANDLE_OPERAND(vvvvRegister) HANDLE_OPERAND(vvvvRegister)
if (HasEVEX_K)
HANDLE_OPERAND(writemaskRegister)
HANDLE_OPERAND(memory) HANDLE_OPERAND(memory)
HANDLE_OPTIONAL(relocation) HANDLE_OPTIONAL(relocation)
break; break;