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Oop - r150653 + r150654 broke one of my test cases. Backing out for now...

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150655 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Lang Hames 2012-02-16 02:32:10 +00:00
parent afae28b1c6
commit 1834df8384
2 changed files with 4 additions and 9 deletions
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12
lib/CodeGen/MachineCSE.cpp
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@ -63,8 +63,6 @@ namespace {
virtual void releaseMemory() {
ScopeMap.clear();
Exps.clear();
AllocatableRegs.clear();
ReservedRegs.clear();
}
private:
@ -78,8 +76,6 @@ namespace {
ScopedHTType VNT;
SmallVector<MachineInstr*, 64> Exps;
unsigned CurrVN;
BitVector AllocatableRegs;
BitVector ReservedRegs;
bool PerformTrivialCoalescing(MachineInstr *MI, MachineBasicBlock *MBB);
bool isPhysDefTriviallyDead(unsigned Reg,
@ -240,9 +236,9 @@ bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
return false;
for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
if (AllocatableRegs.test(PhysDefs[i]) || ReservedRegs.test(PhysDefs[i]))
// Avoid extending live range of physical registers if they are
//allocatable or reserved.
if (TRI->isInAllocatableClass(PhysDefs[i]))
// Avoid extending live range of physical registers unless
// they are unallocatable.
return false;
}
CrossMBB = true;
@ -592,7 +588,5 @@ bool MachineCSE::runOnMachineFunction(MachineFunction &MF) {
MRI = &MF.getRegInfo();
AA = &getAnalysis<AliasAnalysis>();
DT = &getAnalysis<MachineDominatorTree>();
AllocatableRegs = TRI->getAllocatableSet(MF);
ReservedRegs = TRI->getReservedRegs(MF);
return PerformCSE(DT->getRootNode());
}

1
lib/Target/ARM/ARMBaseRegisterInfo.cpp
View File

@ -79,6 +79,7 @@ getReservedRegs(const MachineFunction &MF) const {
BitVector Reserved(getNumRegs());
Reserved.set(ARM::SP);
Reserved.set(ARM::PC);
Reserved.set(ARM::FPSCR);
if (TFI->hasFP(MF))
Reserved.set(FramePtr);
if (hasBasePointer(MF))