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[X86][Haswell][SchedModel] Add architecture specific scheduling models.

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Group: Integer instructions.
Sub-group: Synchronization instructions.

<rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215909 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Quentin Colombet 2014-08-18 17:55:21 +00:00
parent 2a2fcc1a0e
commit 184c0f8b2f
1 changed files with 26 additions and 0 deletions
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26
lib/Target/X86/X86SchedHaswell.td
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@ -916,4 +916,30 @@ def WriteCMPS : SchedWriteRes<[HWPort23, HWPort0156]> {
}
def : InstRW<[WriteCMPS], (instregex "CMPS(B|L|Q|W)")>;
//-- Synchronization instructions --//
// XADD.
def WriteXADD : SchedWriteRes<[]> {
let NumMicroOps = 5;
}
def : InstRW<[WriteXADD], (instregex "XADD(8|16|32|64)rm")>;
// CMPXCHG.
def WriteCMPXCHG : SchedWriteRes<[]> {
let NumMicroOps = 6;
}
def : InstRW<[WriteCMPXCHG], (instregex "CMPXCHG(8|16|32|64)rm")>;
// CMPXCHG8B.
def WriteCMPXCHG8B : SchedWriteRes<[]> {
let NumMicroOps = 15;
}
def : InstRW<[WriteCMPXCHG8B], (instregex "CMPXCHG8B")>;
// CMPXCHG16B.
def WriteCMPXCHG16B : SchedWriteRes<[]> {
let NumMicroOps = 22;
}
def : InstRW<[WriteCMPXCHG16B], (instregex "CMPXCHG16B")>;
} // SchedModel