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[mips][msa] Matheus Almeida pointed out a silly mistake in r188893. Fixed it.

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I accidentally changed the encoding of the MSA registers to zero instead of 0
to 31. This change restores the encoding the registers had prior to r188893.

This didn't show up in the existing tests because direct-object emission isn't
implemented yet for MSA.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188896 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders 2013-08-21 09:09:52 +00:00
parent d95865a2a2
commit 187dedf21d
1 changed files with 1 additions and 1 deletions
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2
lib/Target/Mips/MipsRegisterInfo.td
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@ -174,7 +174,7 @@ let Namespace = "Mips" in {
/// Mips MSA registers
/// MSA and FPU cannot both be present unless the FPU has 64-bit registers
foreach I = 0-31 in
def W#I : AFPR128<0, "w"#I, [!cast<AFPR64>("D"#I#"_64")]>,
def W#I : AFPR128<I, "w"#I, [!cast<AFPR64>("D"#I#"_64")]>,
DwarfRegNum<[!add(I, 32)]>;
// Hi/Lo registers