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In the case of an extractelement on an insertelement value,
the element indices may be equal if either one is not a constant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63311 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2597,9 +2597,13 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
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// EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector
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// operations are lowered to scalars.
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if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) {
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// If the indices are the same, return the inserted element.
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if (N1.getOperand(2) == N2)
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return N1.getOperand(1);
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else
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// If the indices are known different, extract the element from
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// the original vector.
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else if (isa<ConstantSDNode>(N1.getOperand(2)) &&
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isa<ConstantSDNode>(N2))
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return getNode(ISD::EXTRACT_VECTOR_ELT, VT, N1.getOperand(0), N2);
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}
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break;
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25
test/CodeGen/X86/vec_ins_extract-1.ll
Normal file
25
test/CodeGen/X86/vec_ins_extract-1.ll
Normal file
@ -0,0 +1,25 @@
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; RUN: llvm-as < %s | llc -march=x86 | grep {(%esp,%eax,4)} | count 4
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; Inserts and extracts with variable indices must be lowered
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; to memory accesses.
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define i32 @t0(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
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%t13 = insertelement <4 x i32> %t8, i32 76, i32 %t7
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%t9 = extractelement <4 x i32> %t13, i32 0
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ret i32 %t9
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}
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define i32 @t1(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
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%t13 = insertelement <4 x i32> %t8, i32 76, i32 0
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%t9 = extractelement <4 x i32> %t13, i32 %t7
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ret i32 %t9
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}
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define <4 x i32> @t2(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
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%t9 = extractelement <4 x i32> %t8, i32 %t7
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%t13 = insertelement <4 x i32> %t8, i32 %t9, i32 0
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ret <4 x i32> %t13
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}
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define <4 x i32> @t3(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
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%t9 = extractelement <4 x i32> %t8, i32 0
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%t13 = insertelement <4 x i32> %t8, i32 %t9, i32 %t7
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ret <4 x i32> %t13
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}
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