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Only insert an AND when converting from BR_COND to BRCC if needed.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25832 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-01-31 05:04:52 +00:00
parent ef6ffb17c7
commit 19c5c4cca9
1 changed files with 3 additions and 1 deletions
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4
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -703,7 +703,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
} else {
// Make sure the condition is either zero or one. It may have been
// promoted from something else.
Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
unsigned NumBits = MVT::getSizeInBits(Tmp2.getValueType());
if (!TLI.MaskedValueIsZero(Tmp2, (~0ULL >> (64-NumBits))^1))
Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
DAG.getCondCode(ISD::SETNE), Tmp2,