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https://github.com/c64scene-ar/llvm-6502.git
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start adding MRMDestMem, which requires memory form mod/rm encoding
to start limping. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95350 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
28249d98e1
commit
1ac23b1038
@ -25,9 +25,12 @@ class X86MCCodeEmitter : public MCCodeEmitter {
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void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
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const TargetMachine &TM;
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const TargetInstrInfo &TII;
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bool Is64BitMode;
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public:
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X86MCCodeEmitter(TargetMachine &tm)
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: TM(tm), TII(*TM.getInstrInfo()) {
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// FIXME: Get this from the right place.
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Is64BitMode = false;
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}
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~X86MCCodeEmitter() {}
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@ -59,6 +62,9 @@ public:
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EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), OS);
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}
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void EmitMemModRMByte(const MCInst &MI, unsigned Op,
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unsigned RegOpcodeField, intptr_t PCAdj,
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raw_ostream &OS) const;
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void EncodeInstruction(const MCInst &MI, raw_ostream &OS) const;
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@ -73,6 +79,143 @@ MCCodeEmitter *llvm::createX86MCCodeEmitter(const Target &,
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}
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/// isDisp8 - Return true if this signed displacement fits in a 8-bit
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/// sign-extended field.
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static bool isDisp8(int Value) {
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return Value == (signed char)Value;
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}
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void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
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unsigned RegOpcodeField,
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intptr_t PCAdj,
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raw_ostream &OS) const {
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const MCOperand &Op3 = MI.getOperand(Op+3);
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int DispVal = 0;
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const MCOperand *DispForReloc = 0;
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// Figure out what sort of displacement we have to handle here.
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if (Op3.isImm()) {
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DispVal = Op3.getImm();
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} else {
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#if 0
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if (Op3.isGlobal()) {
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DispForReloc = &Op3;
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} else if (Op3.isSymbol()) {
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DispForReloc = &Op3;
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} else if (Op3.isCPI()) {
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if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) {
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DispForReloc = &Op3;
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} else {
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DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex());
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DispVal += Op3.getOffset();
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}
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} else {
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assert(Op3.isJTI());
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if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) {
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DispForReloc = &Op3;
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} else {
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DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex());
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}
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#endif
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}
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const MCOperand &Base = MI.getOperand(Op);
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//const MCOperand &Scale = MI.getOperand(Op+1);
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const MCOperand &IndexReg = MI.getOperand(Op+2);
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unsigned BaseReg = Base.getReg();
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// Is a SIB byte needed?
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// If no BaseReg, issue a RIP relative instruction only if the MCE can
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// resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
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// 2-7) and absolute references.
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if ((!Is64BitMode || DispForReloc || BaseReg != 0) &&
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IndexReg.getReg() == 0 &&
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(BaseReg == X86::RIP || (BaseReg != 0 && BaseReg != X86::ESP))) {
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if (BaseReg == 0 || BaseReg == X86::RIP) { // Just a displacement?
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// Emit special case [disp32] encoding
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EmitByte(ModRMByte(0, RegOpcodeField, 5), OS);
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#if 0
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emitDisplacementField(DispForReloc, DispVal, PCAdj, true);
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#endif
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} else {
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unsigned BaseRegNo = GetX86RegNum(Base);
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if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
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// Emit simple indirect register encoding... [EAX] f.e.
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EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), OS);
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} else if (!DispForReloc && isDisp8(DispVal)) {
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// Emit the disp8 encoding... [REG+disp8]
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EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), OS);
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EmitConstant(DispVal, 1, OS);
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} else {
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// Emit the most general non-SIB encoding: [REG+disp32]
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EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), OS);
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#if 0
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emitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel);
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#endif
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}
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}
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} else { // We need a SIB byte, so start by outputting the ModR/M byte first
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assert(IndexReg.getReg() != X86::ESP &&
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IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
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bool ForceDisp32 = false;
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bool ForceDisp8 = false;
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if (BaseReg == 0) {
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// If there is no base register, we emit the special case SIB byte with
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// MOD=0, BASE=5, to JUST get the index, scale, and displacement.
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EmitByte(ModRMByte(0, RegOpcodeField, 4), OS);
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ForceDisp32 = true;
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} else if (DispForReloc) {
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// Emit the normal disp32 encoding.
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EmitByte(ModRMByte(2, RegOpcodeField, 4), OS);
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ForceDisp32 = true;
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} else if (DispVal == 0 && BaseReg != X86::EBP) {
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// Emit no displacement ModR/M byte
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EmitByte(ModRMByte(0, RegOpcodeField, 4), OS);
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} else if (isDisp8(DispVal)) {
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// Emit the disp8 encoding.
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EmitByte(ModRMByte(1, RegOpcodeField, 4), OS);
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ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
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} else {
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// Emit the normal disp32 encoding.
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EmitByte(ModRMByte(2, RegOpcodeField, 4), OS);
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}
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#if 0
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// Calculate what the SS field value should be...
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static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
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unsigned SS = SSTable[Scale.getImm()];
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if (BaseReg == 0) {
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// Handle the SIB byte for the case where there is no base, see Intel
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// Manual 2A, table 2-7. The displacement has already been output.
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unsigned IndexRegNo;
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if (IndexReg.getReg())
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IndexRegNo = getX86RegNum(IndexReg.getReg());
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else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
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IndexRegNo = 4;
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emitSIBByte(SS, IndexRegNo, 5);
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} else {
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unsigned BaseRegNo = getX86RegNum(BaseReg);
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unsigned IndexRegNo;
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if (IndexReg.getReg())
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IndexRegNo = getX86RegNum(IndexReg.getReg());
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else
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IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
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emitSIBByte(SS, IndexRegNo, BaseRegNo);
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}
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// Do we need to output a displacement?
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if (ForceDisp8) {
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emitConstant(DispVal, 1);
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} else if (DispVal != 0 || ForceDisp32) {
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emitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel);
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}
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#endif
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}
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}
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void X86MCCodeEmitter::
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EncodeInstruction(const MCInst &MI, raw_ostream &OS) const {
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@ -175,9 +318,12 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS) const {
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// Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
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--NumOps;
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// FIXME: Can we kill off MRMInitReg??
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unsigned char BaseOpcode = X86InstrInfo::getBaseOpcodeFor(Desc);
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switch (TSFlags & X86II::FormMask) {
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default: assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
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default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
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assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
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case X86II::RawFrm: {
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EmitByte(BaseOpcode, OS);
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@ -213,6 +359,17 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS) const {
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EmitConstant(MI.getOperand(CurOp++).getImm(),
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X86InstrInfo::sizeOfImm(&Desc), OS);
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break;
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case X86II::MRMDestMem:
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EmitByte(BaseOpcode, OS);
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EmitMemModRMByte(MI, CurOp,
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GetX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)),
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0, OS);
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CurOp += X86AddrNumOperands + 1;
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if (CurOp != NumOps)
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EmitConstant(MI.getOperand(CurOp++).getImm(),
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X86InstrInfo::sizeOfImm(&Desc), OS);
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break;
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}
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#ifndef NDEBUG
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