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Make changes necessary for supporting floating point load and store instructions

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that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141623 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2011-10-11 01:12:52 +00:00
parent 142bd1a54e
commit 1acb7df498
4 changed files with 50 additions and 23 deletions
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6
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -11,12 +11,6 @@
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Mips64 Instruction Predicate Definitions.
//===----------------------------------------------------------------------===//
def HasMips64 : Predicate<"Subtarget.hasMips64()">;
def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">;
//===----------------------------------------------------------------------===//
// Mips Operand, Complex Patterns and Transformations Definitions.
//===----------------------------------------------------------------------===//

40
lib/Target/Mips/MipsInstrFPU.td
View File

@ -73,6 +73,18 @@ def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">;
// Only S32 and D32 are supported right now.
//===----------------------------------------------------------------------===//
// FP load.
class FPLoad<bits<6> op, string opstr, PatFrag FOp, RegisterClass RC,
Operand MemOpnd>:
FFI<op, (outs RC:$ft), (ins MemOpnd:$base),
!strconcat(opstr, "\t$ft, $base"), [(set RC:$ft, (FOp addr:$base))]>;
// FP store.
class FPStore<bits<6> op, string opstr, PatFrag FOp, RegisterClass RC,
Operand MemOpnd>:
FFI<op, (outs), (ins RC:$ft, MemOpnd:$base),
!strconcat(opstr, "\t$ft, $base"), [(store RC:$ft, addr:$base)]>;
// Instructions that convert an FP value to 32-bit fixed point.
multiclass FFR1_W_M<bits<6> funct, string opstr> {
def _S : FFR1<funct, 16, opstr, "w.s", FGR32, FGR32>;
@ -170,19 +182,25 @@ def FMOV_D64 : FFR1<0x6, 17, "mov", "d", FGR64, FGR64>,
Requires<[IsFP64bit]>;
/// Floating Point Memory Instructions
let Predicates = [IsNotSingleFloat] in {
def LDC1 : FFI<0b110101, (outs AFGR64:$ft), (ins mem:$addr),
"ldc1\t$ft, $addr", [(set AFGR64:$ft, (load addr:$addr))]>;
def SDC1 : FFI<0b111101, (outs), (ins AFGR64:$ft, mem:$addr),
"sdc1\t$ft, $addr", [(store AFGR64:$ft, addr:$addr)]>;
let Predicates = [IsN64] in {
def LWC1_P8 : FPLoad<0x31, "lwc1", load, FGR32, mem64>;
def SWC1_P8 : FPStore<0x39, "swc1", store, FGR32, mem64>;
def LDC164_P8 : FPLoad<0x35, "ldc1", load, FGR64, mem64>;
def SDC164_P8 : FPStore<0x3d, "sdc1", store, FGR64, mem64>;
}
// LWC1 and SWC1 can always be emitted with odd registers.
def LWC1 : FFI<0b110001, (outs FGR32:$ft), (ins mem:$addr), "lwc1\t$ft, $addr",
[(set FGR32:$ft, (load addr:$addr))]>;
def SWC1 : FFI<0b111001, (outs), (ins FGR32:$ft, mem:$addr),
"swc1\t$ft, $addr", [(store FGR32:$ft, addr:$addr)]>;
let Predicates = [NotN64] in {
def LWC1 : FPLoad<0x31, "lwc1", load, FGR32, mem>;
def SWC1 : FPStore<0x39, "swc1", store, FGR32, mem>;
let Predicates = [HasMips64] in {
def LDC164 : FPLoad<0x35, "ldc1", load, FGR64, mem>;
def SDC164 : FPStore<0x3d, "sdc1", store, FGR64, mem>;
}
let Predicates = [NotMips64] in {
def LDC1 : FPLoad<0x35, "ldc1", load, AFGR64, mem>;
def SDC1 : FPStore<0x3d, "sdc1", store, AFGR64, mem>;
}
}
/// Floating-point Aritmetic
defm FADD : FFR2P_M<0x10, "add", fadd, 1>;

24
lib/Target/Mips/MipsInstrInfo.cpp
View File

@ -48,8 +48,12 @@ static bool isZeroImm(const MachineOperand &op) {
unsigned MipsInstrInfo::
isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
{
if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
(MI->getOpcode() == Mips::LDC1)) {
unsigned Opc = MI->getOpcode();
if ((Opc == Mips::LW) || (Opc == Mips::LW_P8) || (Opc == Mips::LD) ||
(Opc == Mips::LD_P8) || (Opc == Mips::LWC1) || (Opc == Mips::LWC1_P8) ||
(Opc == Mips::LDC1) || (Opc == Mips::LDC164) ||
(Opc == Mips::LDC164_P8)) {
if ((MI->getOperand(1).isFI()) && // is a stack slot
(MI->getOperand(2).isImm()) && // the imm is zero
(isZeroImm(MI->getOperand(2)))) {
@ -69,8 +73,12 @@ isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
unsigned MipsInstrInfo::
isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
{
if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
(MI->getOpcode() == Mips::SDC1)) {
unsigned Opc = MI->getOpcode();
if ((Opc == Mips::SW) || (Opc == Mips::SW_P8) || (Opc == Mips::SD) ||
(Opc == Mips::SD_P8) || (Opc == Mips::SWC1) || (Opc == Mips::SWC1_P8) ||
(Opc == Mips::SDC1) || (Opc == Mips::SDC164) ||
(Opc == Mips::SDC164_P8)) {
if ((MI->getOperand(1).isFI()) && // is a stack slot
(MI->getOperand(2).isImm()) && // the imm is zero
(isZeroImm(MI->getOperand(2)))) {
@ -168,9 +176,11 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
else if (RC == Mips::CPU64RegsRegisterClass)
Opc = IsN64 ? Mips::SD_P8 : Mips::SD;
else if (RC == Mips::FGR32RegisterClass)
Opc = Mips::SWC1;
Opc = IsN64 ? Mips::SWC1_P8 : Mips::SWC1;
else if (RC == Mips::AFGR64RegisterClass)
Opc = Mips::SDC1;
else if (RC == Mips::FGR64RegisterClass)
Opc = IsN64 ? Mips::SDC164_P8 : Mips::SDC164;
assert(Opc && "Register class not handled!");
BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
@ -192,9 +202,11 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
else if (RC == Mips::CPU64RegsRegisterClass)
Opc = IsN64 ? Mips::LD_P8 : Mips::LD;
else if (RC == Mips::FGR32RegisterClass)
Opc = Mips::LWC1;
Opc = IsN64 ? Mips::LWC1_P8 : Mips::LWC1;
else if (RC == Mips::AFGR64RegisterClass)
Opc = Mips::LDC1;
else if (RC == Mips::FGR64RegisterClass)
Opc = IsN64 ? Mips::LDC164_P8 : Mips::LDC164;
assert(Opc && "Register class not handled!");
BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0);

3
lib/Target/Mips/MipsInstrInfo.td
View File

@ -127,6 +127,9 @@ def HasSwap : Predicate<"Subtarget.hasSwap()">;
def HasCondMov : Predicate<"Subtarget.hasCondMov()">;
def HasMips32 : Predicate<"Subtarget.hasMips32()">;
def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">;
def HasMips64 : Predicate<"Subtarget.hasMips64()">;
def NotMips64 : Predicate<"!Subtarget.hasMips64()">;
def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">;
def IsN64 : Predicate<"Subtarget.isABI_N64()">;
def NotN64 : Predicate<"!Subtarget.isABI_N64()">;