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Intel syntax: Robustify register parsing.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148591 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Devang Patel
2012-01-20 22:32:05 +00:00
parent a3c4ca9c7b
commit 1aea430b88
2 changed files with 18 additions and 28 deletions
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44
lib/Target/X86/AsmParser/X86AsmParser.cpp
View File

@@ -470,17 +470,20 @@ bool X86AsmParser::isDstOp(X86Operand &Op) {
bool X86AsmParser::ParseRegister(unsigned &RegNo, bool X86AsmParser::ParseRegister(unsigned &RegNo,
SMLoc &StartLoc, SMLoc &EndLoc) { SMLoc &StartLoc, SMLoc &EndLoc) {
RegNo = 0; RegNo = 0;
const AsmToken &TokPercent = Parser.getTok(); bool IntelSyntax = getParser().getAssemblerDialect();
if (!getParser().getAssemblerDialect()) { if (!IntelSyntax) {
const AsmToken &TokPercent = Parser.getTok();
assert(TokPercent.is(AsmToken::Percent) && "Invalid token kind!"); assert(TokPercent.is(AsmToken::Percent) && "Invalid token kind!");
StartLoc = TokPercent.getLoc(); StartLoc = TokPercent.getLoc();
Parser.Lex(); // Eat percent token. Parser.Lex(); // Eat percent token.
} }
const AsmToken &Tok = Parser.getTok(); const AsmToken &Tok = Parser.getTok();
if (Tok.isNot(AsmToken::Identifier)) if (Tok.isNot(AsmToken::Identifier)) {
if (IntelSyntax) return true;
return Error(StartLoc, "invalid register name", return Error(StartLoc, "invalid register name",
SMRange(StartLoc, Tok.getEndLoc())); SMRange(StartLoc, Tok.getEndLoc()));
}
RegNo = MatchRegisterName(Tok.getString()); RegNo = MatchRegisterName(Tok.getString());
@@ -560,9 +563,11 @@ bool X86AsmParser::ParseRegister(unsigned &RegNo,
} }
} }
if (RegNo == 0) if (RegNo == 0) {
if (IntelSyntax) return true;
return Error(StartLoc, "invalid register name", return Error(StartLoc, "invalid register name",
SMRange(StartLoc, Tok.getEndLoc())); SMRange(StartLoc, Tok.getEndLoc()));
}
EndLoc = Tok.getEndLoc(); EndLoc = Tok.getEndLoc();
Parser.Lex(); // Eat identifier token. Parser.Lex(); // Eat identifier token.
@@ -575,16 +580,6 @@ X86Operand *X86AsmParser::ParseOperand() {
return ParseATTOperand(); return ParseATTOperand();
} }
/// getIntelRegister - If this is an intel register operand
/// then return register number, otherwise return 0;
static unsigned getIntelRegisterOperand(StringRef Str) {
unsigned RegNo = MatchRegisterName(Str);
// If the match failed, try the register name as lowercase.
if (RegNo == 0)
RegNo = MatchRegisterName(Str.lower());
return RegNo;
}
/// getIntelMemOperandSize - Return intel memory operand size. /// getIntelMemOperandSize - Return intel memory operand size.
static unsigned getIntelMemOperandSize(StringRef OpStr) { static unsigned getIntelMemOperandSize(StringRef OpStr) {
unsigned Size = 0; unsigned Size = 0;
@@ -613,10 +608,7 @@ X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned Size) {
if (getLexer().is(AsmToken::Identifier)) { if (getLexer().is(AsmToken::Identifier)) {
// Parse BaseReg // Parse BaseReg
BaseReg = getIntelRegisterOperand(Tok.getString()); if (ParseRegister(BaseReg, Start, End)) {
if (BaseReg)
Parser.Lex();
else {
// Handle '[' 'symbol' ']' // Handle '[' 'symbol' ']'
const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext()); const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
if (getParser().ParseExpression(Disp, End)) return 0; if (getParser().ParseExpression(Disp, End)) return 0;
@@ -645,20 +637,16 @@ X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned Size) {
if (getLexer().is(AsmToken::Star)) { if (getLexer().is(AsmToken::Star)) {
Parser.Lex(); Parser.Lex();
SMLoc IdxRegLoc = Parser.getTok().getLoc(); SMLoc IdxRegLoc = Parser.getTok().getLoc();
IndexReg = getIntelRegisterOperand(Parser.getTok().getString()); if (ParseRegister(IndexReg, IdxRegLoc, End))
if (!IndexReg) return ErrorOperand(IdxRegLoc, "Expected register"); return ErrorOperand(IdxRegLoc, "Expected register");
Parser.Lex(); // Eat register
Scale = Val; Scale = Val;
} else if (getLexer().is(AsmToken::RBrac)) { } else if (getLexer().is(AsmToken::RBrac)) {
const MCExpr *ValExpr = MCConstantExpr::Create(Val, getContext()); const MCExpr *ValExpr = MCConstantExpr::Create(Val, getContext());
Disp = isPlus ? ValExpr : MCConstantExpr::Create(0-Val, getContext()); Disp = isPlus ? ValExpr : MCConstantExpr::Create(0-Val, getContext());
} else } else
return ErrorOperand(PlusLoc, "unexpected token after +"); return ErrorOperand(PlusLoc, "unexpected token after +");
} else if (getLexer().is(AsmToken::Identifier)) { } else if (getLexer().is(AsmToken::Identifier))
IndexReg = getIntelRegisterOperand(Tok.getString()); ParseRegister(IndexReg, Start, End);
if (IndexReg)
Parser.Lex();
}
} }
if (getLexer().isNot(AsmToken::RBrac)) if (getLexer().isNot(AsmToken::RBrac))
@@ -713,8 +701,8 @@ X86Operand *X86AsmParser::ParseIntelOperand() {
} }
// register // register
if(unsigned RegNo = getIntelRegisterOperand(TokenString)) { unsigned RegNo = 0;
Parser.Lex(); if (!ParseRegister(RegNo, Start, End)) {
End = Parser.getTok().getLoc(); End = Parser.getTok().getLoc();
return X86Operand::CreateReg(RegNo, Start, End); return X86Operand::CreateReg(RegNo, Start, End);
} }

2
test/MC/X86/intel-syntax.s
View File

@@ -53,4 +53,6 @@ _main:
and rax, 257 and rax, 257
// CHECK: andq $-257, %rax // CHECK: andq $-257, %rax
and rax, -257 and rax, -257
// CHECK: fld %st(0)
fld ST(0)
ret ret