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Support register masks in MachineLICM.
Only PostRA LICM is affected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148589 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -163,7 +163,9 @@ namespace {
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/// ProcessMI - Examine the instruction for potentai LICM candidate. Also
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/// gather register def and frame object update information.
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void ProcessMI(MachineInstr *MI, unsigned *PhysRegDefs,
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void ProcessMI(MachineInstr *MI,
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BitVector &PhysRegDefs,
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BitVector &PhysRegClobbers,
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SmallSet<int, 32> &StoredFIs,
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SmallVector<CandidateInfo, 32> &Candidates);
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@ -392,7 +394,8 @@ static bool InstructionStoresToFI(const MachineInstr *MI, int FI) {
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/// ProcessMI - Examine the instruction for potentai LICM candidate. Also
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/// gather register def and frame object update information.
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void MachineLICM::ProcessMI(MachineInstr *MI,
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unsigned *PhysRegDefs,
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BitVector &PhysRegDefs,
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BitVector &PhysRegClobbers,
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SmallSet<int, 32> &StoredFIs,
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SmallVector<CandidateInfo, 32> &Candidates) {
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bool RuledOut = false;
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@ -411,6 +414,16 @@ void MachineLICM::ProcessMI(MachineInstr *MI,
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continue;
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}
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// We can't hoist an instruction defining a physreg that is clobbered in
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// the loop.
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if (MO.isRegMask()) {
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if (const uint32_t *Mask = MO.getRegMask())
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PhysRegClobbers.setBitsNotInMask(Mask);
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else
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PhysRegClobbers.set();
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continue;
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}
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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@ -420,7 +433,7 @@ void MachineLICM::ProcessMI(MachineInstr *MI,
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"Not expecting virtual register!");
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if (!MO.isDef()) {
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if (Reg && PhysRegDefs[Reg])
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if (Reg && (PhysRegDefs.test(Reg) || PhysRegClobbers.test(Reg)))
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// If it's using a non-loop-invariant register, then it's obviously not
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// safe to hoist.
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HasNonInvariantUse = true;
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@ -428,9 +441,8 @@ void MachineLICM::ProcessMI(MachineInstr *MI,
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}
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if (MO.isImplicit()) {
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++PhysRegDefs[Reg];
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for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
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++PhysRegDefs[*AS];
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for (const unsigned *AS = TRI->getOverlaps(Reg); *AS; ++AS)
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PhysRegClobbers.set(*AS);
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if (!MO.isDead())
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// Non-dead implicit def? This cannot be hoisted.
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RuledOut = true;
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@ -447,14 +459,17 @@ void MachineLICM::ProcessMI(MachineInstr *MI,
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Def = Reg;
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// If we have already seen another instruction that defines the same
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// register, then this is not safe.
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if (++PhysRegDefs[Reg] > 1)
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// MI defined register is seen defined by another instruction in
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// the loop, it cannot be a LICM candidate.
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RuledOut = true;
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for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
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if (++PhysRegDefs[*AS] > 1)
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// register, then this is not safe. Two defs is indicated by setting a
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// PhysRegClobbers bit.
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for (const unsigned *AS = TRI->getOverlaps(Reg); *AS; ++AS) {
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if (PhysRegDefs.test(Reg))
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PhysRegClobbers.set(Reg);
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if (PhysRegClobbers.test(Reg))
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// MI defined register is seen defined by another instruction in
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// the loop, it cannot be a LICM candidate.
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RuledOut = true;
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PhysRegDefs.set(Reg);
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}
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}
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// Only consider reloads for now and remats which do not have register
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@ -471,8 +486,8 @@ void MachineLICM::ProcessMI(MachineInstr *MI,
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/// invariants out to the preheader.
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void MachineLICM::HoistRegionPostRA() {
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unsigned NumRegs = TRI->getNumRegs();
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unsigned *PhysRegDefs = new unsigned[NumRegs];
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std::fill(PhysRegDefs, PhysRegDefs + NumRegs, 0);
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BitVector PhysRegDefs(NumRegs); // Regs defined once in the loop.
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BitVector PhysRegClobbers(NumRegs); // Regs defined more than once.
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SmallVector<CandidateInfo, 32> Candidates;
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SmallSet<int, 32> StoredFIs;
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@ -494,16 +509,15 @@ void MachineLICM::HoistRegionPostRA() {
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for (MachineBasicBlock::livein_iterator I = BB->livein_begin(),
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E = BB->livein_end(); I != E; ++I) {
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unsigned Reg = *I;
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++PhysRegDefs[Reg];
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for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
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++PhysRegDefs[*AS];
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for (const unsigned *AS = TRI->getOverlaps(Reg); *AS; ++AS)
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PhysRegDefs.set(*AS);
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}
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SpeculationState = SpeculateUnknown;
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for (MachineBasicBlock::iterator
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MII = BB->begin(), E = BB->end(); MII != E; ++MII) {
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MachineInstr *MI = &*MII;
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ProcessMI(MI, PhysRegDefs, StoredFIs, Candidates);
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ProcessMI(MI, PhysRegDefs, PhysRegClobbers, StoredFIs, Candidates);
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}
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}
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@ -517,14 +531,15 @@ void MachineLICM::HoistRegionPostRA() {
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StoredFIs.count(Candidates[i].FI))
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continue;
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if (PhysRegDefs[Candidates[i].Def] == 1) {
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if (!PhysRegClobbers.test(Candidates[i].Def)) {
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bool Safe = true;
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MachineInstr *MI = Candidates[i].MI;
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for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) {
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const MachineOperand &MO = MI->getOperand(j);
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if (!MO.isReg() || MO.isDef() || !MO.getReg())
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continue;
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if (PhysRegDefs[MO.getReg()]) {
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if (PhysRegDefs.test(MO.getReg()) ||
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PhysRegClobbers.test(MO.getReg())) {
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// If it's using a non-loop-invariant register, then it's obviously
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// not safe to hoist.
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Safe = false;
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@ -535,8 +550,6 @@ void MachineLICM::HoistRegionPostRA() {
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HoistPostRA(MI, Candidates[i].Def);
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}
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}
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delete[] PhysRegDefs;
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}
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/// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the current
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