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[mips] Add (setne $lhs, 0) instruction selection pattern.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182307 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2013-05-20 18:18:07 +00:00
parent f894199a14
commit 1aeb13bd9c
2 changed files with 12 additions and 0 deletions
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2
lib/Target/Mips/MipsInstrInfo.td
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@ -1282,6 +1282,8 @@ multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
Instruction SLTuOp, Register ZEROReg> {
def : MipsPat<(seteq RC:$lhs, 0),
(SLTiuOp RC:$lhs, 1)>;
def : MipsPat<(setne RC:$lhs, 0),
(SLTuOp ZEROReg, RC:$lhs)>;
def : MipsPat<(seteq RC:$lhs, RC:$rhs),
(SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
def : MipsPat<(setne RC:$lhs, RC:$rhs),

10
test/CodeGen/Mips/setcc-se.ll
View File

@ -9,3 +9,13 @@ entry:
%conv = zext i1 %cmp to i32
ret i32 %conv
}
; CHECK: setne0:
; CHECK: sltu ${{[0-9]+}}, $zero, $4
define i32 @setne0(i32 %a) {
entry:
%cmp = icmp ne i32 %a, 0
%conv = zext i1 %cmp to i32
ret i32 %conv
}