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Expand and rewrite comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189998 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1,7 +1,8 @@
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; RUN: llc < %s -mcpu=swift -mtriple=armv7s-apple-ios | FileCheck %s
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; vldm with registers not aligned with q registers need more micro-ops so that
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; so that there usage becomes unbeneficial on swift.
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; Check that we avoid producing vldm instructions using d registers that
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; begin in the most-significant half of a q register. These require more
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; micro-ops on swift and so aren't worth combining.
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; CHECK-LABEL: test_vldm
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; CHECK: vldmia r{{[0-9]+}}, {d2, d3, d4}
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@ -19,7 +20,7 @@ entry:
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%d2 = load double * %addr1
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%d3 = load double * %addr2
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%d4 = load double * %addr3
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; We are trying to force x[0-3] in register d1 to d4 so that we can test we
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; We are trying to force x[0-3] in registers d1 to d4 so that we can test we
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; don't form a "vldmia rX, {d1, d2, d3, d4}".
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; We are relying on the calling convention and that register allocation
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; properly coalesces registers.
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