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relax assertion

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27358 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2006-04-02 06:19:46 +00:00
parent 1482b5fc7a
commit 1b5232a937
1 changed files with 4 additions and 1 deletions
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5
lib/CodeGen/SelectionDAG/TargetLowering.cpp
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@@ -935,7 +935,10 @@ void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
uint64_t &KnownZero,
uint64_t &KnownOne,
unsigned Depth) const {
assert(Op.getOpcode() >= ISD::BUILTIN_OP_END &&
assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
Op.getOpcode() == ISD::INTRINSIC_VOID) &&
"Should use MaskedValueIsZero if you don't know whether Op"
" is a target node!");
KnownZero = 0;