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When tracking demanded bits, if any bits from the sext of an SRA are demanded,

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then so is the input sign bit.  This fixes mediabench/g721 on X86.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28166 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2006-05-08 17:22:53 +00:00
parent 17c275ff2c
commit 1b7371331f
1 changed files with 8 additions and 2 deletions
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10
lib/CodeGen/SelectionDAG/TargetLowering.cpp
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@@ -467,8 +467,14 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
HighBits <<= MVT::getSizeInBits(VT) - ShAmt; HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
uint64_t TypeMask = MVT::getIntVTBitMask(VT); uint64_t TypeMask = MVT::getIntVTBitMask(VT);
if (SimplifyDemandedBits(Op.getOperand(0), uint64_t InDemandedMask = (DemandedMask << ShAmt) & TypeMask;
(DemandedMask << ShAmt) & TypeMask,
// If any of the demanded bits are produced by the sign extension, we also
// demand the input sign bit.
if (HighBits & DemandedMask)
InDemandedMask |= MVT::getIntVTSignBit(VT);
if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
KnownZero, KnownOne, TLO, Depth+1)) KnownZero, KnownOne, TLO, Depth+1))
return true; return true;
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");