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Transfer implicit operands when expanding the RET_ReallyLR pseudo instruction.

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When we expand the RET_ReallyLR pseudo instruction we also need to transfer the
implicit operands.

The return register is an implicit operand and without it the liveness
calculation generates an incorrect live-out set for the patchpoint.

This fixes rdar://problem/19068476.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233635 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka 2015-03-30 22:45:56 +00:00
parent b0b7c53ee4
commit 1c8595529b
2 changed files with 53 additions and 3 deletions
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9
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
View File

@ -698,12 +698,15 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
return expandMOVImm(MBB, MBBI, 32);
case AArch64::MOVi64imm:
return expandMOVImm(MBB, MBBI, 64);
case AArch64::RET_ReallyLR:
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::RET))
.addReg(AArch64::LR);
case AArch64::RET_ReallyLR: {
MachineInstrBuilder MIB =
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::RET))
.addReg(AArch64::LR);
transferImpOps(MI, MIB, MIB);
MI.eraseFromParent();
return true;
}
}
return false;
}

47
test/CodeGen/AArch64/stackmap-liveness.ll Normal file
View File

@ -0,0 +1,47 @@
; RUN: llc < %s -mtriple=aarch64-apple-darwin | FileCheck %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps
; CHECK-NEXT: __LLVM_StackMaps:
; Header
; CHECK-NEXT: .byte 1
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .short 0
; Num Functions
; CHECK-NEXT: .long 1
; Num LargeConstants
; CHECK-NEXT: .long 0
; Num Callsites
; CHECK-NEXT: .long 1
; Functions and stack size
; CHECK-NEXT: .quad _stackmap_liveness
; CHECK-NEXT: .quad 16
; Test that the return register is recognized as an live-out.
define i64 @stackmap_liveness(i1 %c) {
; CHECK-LABEL: .long L{{.*}}-_stackmap_liveness
; CHECK-NEXT: .short 0
; CHECK-NEXT: .short 0
; Padding
; CHECK-NEXT: .short 0
; Num LiveOut Entries: 1
; CHECK-NEXT: .short 2
; LiveOut Entry 0: X0
; CHECK-NEXT: .short 0
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .byte 8
; LiveOut Entry 1: SP
; CHECK-NEXT: .short 31
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .byte 8
; Align
; CHECK-NEXT: .align 3
%1 = select i1 %c, i64 1, i64 2
call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 1, i32 32, i8* null, i32 0)
ret i64 %1
}
declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)