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Emit neg.s or neg.d only if -enable-no-nans-fp-math is supplied by user,

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otherwise expand FNEG during legalization.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154546 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2012-04-11 22:59:08 +00:00
parent c12a6e6b53
commit 1cc6333161
3 changed files with 26 additions and 3 deletions
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5
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -216,6 +216,11 @@ MipsTargetLowering(MipsTargetMachine &TM)
setOperationAction(ISD::FREM, MVT::f32, Expand);
setOperationAction(ISD::FREM, MVT::f64, Expand);
if (!TM.Options.NoNaNsFPMath) {
setOperationAction(ISD::FNEG, MVT::f32, Expand);
setOperationAction(ISD::FNEG, MVT::f64, Expand);
}
setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);

7
lib/Target/Mips/MipsInstrFPU.td
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@ -190,9 +190,10 @@ let Predicates = [IsFP64bit] in {
def CVT_D64_L : FFR1<0x21, 21, "cvt", "d.l", FGR64, FGR64>;
}
let Predicates = [NoNaNsFPMath] in
defm FABS : FFR1P_M<0x5, "abs", fabs>;
defm FNEG : FFR1P_M<0x7, "neg", fneg>;
let Predicates = [NoNaNsFPMath] in {
defm FABS : FFR1P_M<0x5, "abs", fabs>;
defm FNEG : FFR1P_M<0x7, "neg", fneg>;
}
defm FSQRT : FFR1P_M<0x4, "sqrt", fsqrt>;
// The odd-numbered registers are only referenced when doing loads,

17
test/CodeGen/Mips/fneg.ll Normal file
View File

@ -0,0 +1,17 @@
; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s
define float @foo0(i32 %a, float %d) nounwind readnone {
entry:
; CHECK-NOT: fabs.s
%sub = fsub float -0.000000e+00, %d
ret float %sub
}
define double @foo1(i32 %a, double %d) nounwind readnone {
entry:
; CHECK: foo1
; CHECK-NOT: fabs.d
; CHECK: jr
%sub = fsub double -0.000000e+00, %d
ret double %sub
}