6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-13 20:32:21 +00:00
Code Issues Projects Releases Wiki Activity

Fix pattern for LD16S_3r, add basic tests to check load / store instructions

Browse Source 
are being properly selected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75797 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne 2009-07-15 17:06:59 +00:00
parent d890de10af
commit 1d05b237a5
3 changed files with 75 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/XCore/XCoreInstrInfo.td
View File

@ -821,7 +821,7 @@ def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)),
(LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
def : Pat<(zextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
def : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
(LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;

39
test/CodeGen/XCore/load.ll Normal file
View File

@ -0,0 +1,39 @@
; RUN: llvm-as < %s | llc -march=xcore > %t1.s
; RUN: not grep add %t1.s
; RUN: not grep ldaw %t1.s
; RUN: not grep lda16 %t1.s
; RUN: not grep zext %t1.s
; RUN: not grep sext %t1.s
; RUN: grep "ldw" %t1.s | count 2
; RUN: grep "ld16s" %t1.s | count 1
; RUN: grep "ld8u" %t1.s | count 1
define i32 @load32(i32* %p, i32 %offset) nounwind {
entry:
%0 = getelementptr i32* %p, i32 %offset
%1 = load i32* %0, align 4
ret i32 %1
}
define i32 @load32_imm(i32* %p) nounwind {
entry:
%0 = getelementptr i32* %p, i32 11
%1 = load i32* %0, align 4
ret i32 %1
}
define i32 @load16(i16* %p, i32 %offset) nounwind {
entry:
%0 = getelementptr i16* %p, i32 %offset
%1 = load i16* %0, align 2
%2 = sext i16 %1 to i32
ret i32 %2
}
define i32 @load8(i8* %p, i32 %offset) nounwind {
entry:
%0 = getelementptr i8* %p, i32 %offset
%1 = load i8* %0, align 1
%2 = zext i8 %1 to i32
ret i32 %2
}

35
test/CodeGen/XCore/store.ll Normal file
View File

@ -0,0 +1,35 @@
; RUN: llvm-as < %s | llc -march=xcore > %t1.s
; RUN: not grep add %t1.s
; RUN: not grep ldaw %t1.s
; RUN: not grep lda16 %t1.s
; RUN: grep "stw" %t1.s | count 2
; RUN: grep "st16" %t1.s | count 1
; RUN: grep "st8" %t1.s | count 1
define void @store32(i32* %p, i32 %offset, i32 %val) nounwind {
entry:
%0 = getelementptr i32* %p, i32 %offset
store i32 %val, i32* %0, align 4
ret void
}
define void @store32_imm(i32* %p, i32 %val) nounwind {
entry:
%0 = getelementptr i32* %p, i32 11
store i32 %val, i32* %0, align 4
ret void
}
define void @store16(i16* %p, i32 %offset, i16 %val) nounwind {
entry:
%0 = getelementptr i16* %p, i32 %offset
store i16 %val, i16* %0, align 2
ret void
}
define void @store8(i8* %p, i32 %offset, i8 %val) nounwind {
entry:
%0 = getelementptr i8* %p, i32 %offset
store i8 %val, i8* %0, align 1
ret void
}