6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-08-05 13:26:55 +00:00
Code Issues Projects Releases Wiki Activity

ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74200 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2009-06-25 20:59:23 +00:00
parent 1af2231da6
commit 1e249e3705
4 changed files with 108 additions and 80 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
test/CodeGen/Thumb2/carry.ll Normal file
View File

@@ -0,0 +1,16 @@
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep "subs r" | count 2
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep adc
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep sbc
define i64 @f1(i64 %a, i64 %b) {
entry:
%tmp = sub i64 %a, %b
ret i64 %tmp
}
define i64 @f2(i64 %a, i64 %b) {
entry:
%tmp1 = shl i64 %a, 1
%tmp2 = sub i64 %tmp1, %b
ret i64 %tmp2
}