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Add support for v1i128 type.

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The v1i128 type is needed for the quadword add/substract instructions introduced
in POWER8. Futhermore, the PowerPC ABI specifies that parameters of type v1i128
are to be passed in a single vector register, while parameters of type i128 are
passed in pairs of GPRs. Thus, it is necessary to be able to differentiate
between v1i128 and i128 in LLVM.

http://reviews.llvm.org/D8564


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235198 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kit Barton 2015-04-17 16:11:05 +00:00
parent fbfd58ab92
commit 1e3da044d8
5 changed files with 52 additions and 41 deletions
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55
include/llvm/CodeGen/MachineValueType.h
View File

@ -26,7 +26,7 @@ namespace llvm {
/// MVT - Machine Value Type. Every type that is supported natively by some
/// processor targeted by LLVM occurs here. This means that any legal value
/// type can be represented by an MVT.
class MVT {
class MVT {
public:
enum SimpleValueType {
// INVALID_SIMPLE_VALUE_TYPE - Simple value types less than zero are
@ -86,22 +86,23 @@ namespace llvm {
v4i64 = 39, // 4 x i64
v8i64 = 40, // 8 x i64
v16i64 = 41, // 16 x i64
v1i128 = 42, // 1 x i128
FIRST_INTEGER_VECTOR_VALUETYPE = v2i1,
LAST_INTEGER_VECTOR_VALUETYPE = v16i64,
LAST_INTEGER_VECTOR_VALUETYPE = v1i128,
v2f16 = 42, // 2 x f16
v4f16 = 43, // 4 x f16
v8f16 = 44, // 8 x f16
v1f32 = 45, // 1 x f32
v2f32 = 46, // 2 x f32
v4f32 = 47, // 4 x f32
v8f32 = 48, // 8 x f32
v16f32 = 49, // 16 x f32
v1f64 = 50, // 1 x f64
v2f64 = 51, // 2 x f64
v4f64 = 52, // 4 x f64
v8f64 = 53, // 8 x f64
v2f16 = 43, // 2 x f16
v4f16 = 44, // 4 x f16
v8f16 = 45, // 8 x f16
v1f32 = 46, // 1 x f32
v2f32 = 47, // 2 x f32
v4f32 = 48, // 4 x f32
v8f32 = 49, // 8 x f32
v16f32 = 50, // 16 x f32
v1f64 = 51, // 1 x f64
v2f64 = 52, // 2 x f64
v4f64 = 53, // 4 x f64
v8f64 = 54, // 8 x f64
FIRST_FP_VECTOR_VALUETYPE = v2f16,
LAST_FP_VECTOR_VALUETYPE = v8f64,
@ -109,18 +110,18 @@ namespace llvm {
FIRST_VECTOR_VALUETYPE = v2i1,
LAST_VECTOR_VALUETYPE = v8f64,
x86mmx = 54, // This is an X86 MMX value
x86mmx = 55, // This is an X86 MMX value
Glue = 55, // This glues nodes together during pre-RA sched
Glue = 56, // This glues nodes together during pre-RA sched
isVoid = 56, // This has no value
isVoid = 57, // This has no value
Untyped = 57, // This value takes a register, but has
Untyped = 58, // This value takes a register, but has
// unspecified type. The register class
// will be determined by the opcode.
FIRST_VALUETYPE = 0, // This is always the beginning of the list.
LAST_VALUETYPE = 58, // This always remains at the end of the list.
LAST_VALUETYPE = 59, // This always remains at the end of the list.
// This is the current maximum for LAST_VALUETYPE.
// MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors
@ -222,10 +223,10 @@ namespace llvm {
/// is128BitVector - Return true if this is a 128-bit vector type.
bool is128BitVector() const {
return (SimpleTy == MVT::v16i8 || SimpleTy == MVT::v8i16 ||
SimpleTy == MVT::v4i32 || SimpleTy == MVT::v2i64 ||
SimpleTy == MVT::v8f16 || SimpleTy == MVT::v4f32 ||
SimpleTy == MVT::v2f64);
return (SimpleTy == MVT::v16i8 || SimpleTy == MVT::v8i16 ||
SimpleTy == MVT::v4i32 || SimpleTy == MVT::v2i64 ||
SimpleTy == MVT::v1i128 || SimpleTy == MVT::v8f16 ||
SimpleTy == MVT::v4f32 || SimpleTy == MVT::v2f64);
}
/// is256BitVector - Return true if this is a 256-bit vector type.
@ -310,6 +311,7 @@ namespace llvm {
case v4i64:
case v8i64:
case v16i64: return i64;
case v1i128: return i128;
case v2f16:
case v4f16:
case v8f16: return f16;
@ -368,6 +370,7 @@ namespace llvm {
case v1i16:
case v1i32:
case v1i64:
case v1i128:
case v1f32:
case v1f64: return 1;
}
@ -427,6 +430,7 @@ namespace llvm {
case v8i16:
case v4i32:
case v2i64:
case v1i128:
case v8f16:
case v4f32:
case v2f64: return 128;
@ -562,6 +566,9 @@ namespace llvm {
if (NumElements == 8) return MVT::v8i64;
if (NumElements == 16) return MVT::v16i64;
break;
case MVT::i128:
if (NumElements == 1) return MVT::v1i128;
break;
case MVT::f16:
if (NumElements == 2) return MVT::v2f16;
if (NumElements == 4) return MVT::v4f16;

33
include/llvm/CodeGen/ValueTypes.td
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@ -62,25 +62,26 @@ def v2i64 : ValueType<128, 38>; // 2 x i64 vector value
def v4i64 : ValueType<256, 39>; // 4 x i64 vector value
def v8i64 : ValueType<512, 40>; // 8 x i64 vector value
def v16i64 : ValueType<1024,41>; // 16 x i64 vector value
def v1i128 : ValueType<128, 42>; // 1 x i128 vector value
def v2f16 : ValueType<32 , 42>; // 2 x f16 vector value
def v4f16 : ValueType<64 , 43>; // 4 x f16 vector value
def v8f16 : ValueType<128, 44>; // 8 x f16 vector value
def v1f32 : ValueType<32 , 45>; // 1 x f32 vector value
def v2f32 : ValueType<64 , 46>; // 2 x f32 vector value
def v4f32 : ValueType<128, 47>; // 4 x f32 vector value
def v8f32 : ValueType<256, 48>; // 8 x f32 vector value
def v16f32 : ValueType<512, 49>; // 16 x f32 vector value
def v1f64 : ValueType<64, 50>; // 1 x f64 vector value
def v2f64 : ValueType<128, 51>; // 2 x f64 vector value
def v4f64 : ValueType<256, 52>; // 4 x f64 vector value
def v8f64 : ValueType<512, 53>; // 8 x f64 vector value
def v2f16 : ValueType<32 , 43>; // 2 x f16 vector value
def v4f16 : ValueType<64 , 44>; // 4 x f16 vector value
def v8f16 : ValueType<128, 45>; // 8 x f16 vector value
def v1f32 : ValueType<32 , 46>; // 1 x f32 vector value
def v2f32 : ValueType<64 , 47>; // 2 x f32 vector value
def v4f32 : ValueType<128, 48>; // 4 x f32 vector value
def v8f32 : ValueType<256, 49>; // 8 x f32 vector value
def v16f32 : ValueType<512, 50>; // 16 x f32 vector value
def v1f64 : ValueType<64, 51>; // 1 x f64 vector value
def v2f64 : ValueType<128, 52>; // 2 x f64 vector value
def v4f64 : ValueType<256, 53>; // 4 x f64 vector value
def v8f64 : ValueType<512, 54>; // 8 x f64 vector value
def x86mmx : ValueType<64 , 54>; // X86 MMX value
def FlagVT : ValueType<0 , 55>; // Pre-RA sched glue
def isVoid : ValueType<0 , 56>; // Produces no value
def untyped: ValueType<8 , 57>; // Produces an untyped value
def x86mmx : ValueType<64 , 55>; // X86 MMX value
def FlagVT : ValueType<0 , 56>; // Pre-RA sched glue
def isVoid : ValueType<0 , 57>; // Produces no value
def untyped: ValueType<8 , 58>; // Produces an untyped value
def MetadataVT: ValueType<0, 250>; // Metadata
// Pseudo valuetype mapped to the current pointer size to any address space.

2
lib/IR/ValueTypes.cpp
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@ -157,6 +157,7 @@ std::string EVT::getEVTString() const {
case MVT::v4i64: return "v4i64";
case MVT::v8i64: return "v8i64";
case MVT::v16i64: return "v16i64";
case MVT::v1i128: return "v1i128";
case MVT::v1f32: return "v1f32";
case MVT::v2f32: return "v2f32";
case MVT::v2f16: return "v2f16";
@ -225,6 +226,7 @@ Type *EVT::getTypeForEVT(LLVMContext &Context) const {
case MVT::v4i64: return VectorType::get(Type::getInt64Ty(Context), 4);
case MVT::v8i64: return VectorType::get(Type::getInt64Ty(Context), 8);
case MVT::v16i64: return VectorType::get(Type::getInt64Ty(Context), 16);
case MVT::v1i128: return VectorType::get(Type::getInt128Ty(Context), 1);
case MVT::v2f16: return VectorType::get(Type::getHalfTy(Context), 2);
case MVT::v4f16: return VectorType::get(Type::getHalfTy(Context), 4);
case MVT::v8f16: return VectorType::get(Type::getHalfTy(Context), 8);

2
test/TableGen/intrinsic-varargs.td
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@ -23,7 +23,7 @@ class Intrinsic<string name, list<LLVMType> param_types = []> {
}
// isVoid needs to match the definition in ValueTypes.td
def isVoid : ValueType<0, 56>; // Produces no value
def isVoid : ValueType<0, 57>; // Produces no value
def llvm_vararg_ty : LLVMType<isVoid>; // this means vararg here
// CHECK: /* 0 */ 0, 28, 0,

1
utils/TableGen/CodeGenTarget.cpp
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@ -99,6 +99,7 @@ std::string llvm::getEnumName(MVT::SimpleValueType T) {
case MVT::v4i64: return "MVT::v4i64";
case MVT::v8i64: return "MVT::v8i64";
case MVT::v16i64: return "MVT::v16i64";
case MVT::v1i128: return "MVT::v1i128";
case MVT::v2f16: return "MVT::v2f16";
case MVT::v4f16: return "MVT::v4f16";
case MVT::v8f16: return "MVT::v8f16";