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https://github.com/c64scene-ar/llvm-6502.git
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[AArch64] Add SchedRW lists to NEON instructions.
Previously, only regular AArch64 instructions were annotated with SchedRW lists. This patch does the same for NEON enabling these instructions to be scheduled by the MIScheduler. Additionally, store operations are now modeled and a few SchedRW lists were updated for bug fixes (e.g. multiple def operands). Reviewers: apazos, mcrosier, atrick Patch by Dave Estes <cestes@codeaurora.org>! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204505 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier
parent
218c7c821b
commit
1eb67a4f84
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@ -463,7 +463,7 @@ defm SUBSww :addsub_exts<0b0, 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR32, subc>,
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(outs GPR32:$Rd)>;
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let Rd = 0b11111, isCompare = 1 in {
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let SchedRW = [WriteCMP, ReadCMP, ReadCMP], Rd = 0b11111, isCompare = 1 in {
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defm CMNx : addsub_exts<0b1, 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>,
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(outs), extends_to_i64>,
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addsub_xxtx< 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>, (outs)>;
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@ -689,7 +689,7 @@ multiclass addsubimm_varieties<string prefix, bit sf, bit op, bits<2> shift,
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[(set NZCV,
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(A64cmp Ty:$Rn, cmp_imm_operand:$Imm12))],
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NoItinerary>,
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Sched<[WriteALU, ReadALU]> {
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Sched<[WriteCMP, ReadCMP]> {
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let Rd = 0b11111;
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let Defs = [NZCV];
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let isCompare = 1;
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@ -1086,7 +1086,7 @@ def BFMwwii :
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A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
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(ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),
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"bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
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Sched<[WriteALU, ReadALU]> {
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Sched<[WriteALU, ReadALU, ReadALU]> {
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let DecoderMethod = "DecodeBitfieldInstruction";
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let Constraints = "$src = $Rd";
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}
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@ -1095,7 +1095,7 @@ def BFMxxii :
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A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
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(ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),
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"bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
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Sched<[WriteALU, ReadALU]> {
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Sched<[WriteALU, ReadALU, ReadALU]> {
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let DecoderMethod = "DecodeBitfieldInstruction";
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let Constraints = "$src = $Rd";
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}
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@ -1295,7 +1295,7 @@ defm UBFX : A64I_bitfield_extract<0b10, "ubfx", A64Ubfx>;
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def BFXILwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
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(ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
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"bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
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Sched<[WriteALU, ReadALU]> {
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Sched<[WriteALU, ReadALU, ReadALU]> {
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// As above, no disassembler allowed.
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let isAsmParserOnly = 1;
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let Constraints = "$src = $Rd";
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@ -1304,7 +1304,7 @@ def BFXILwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
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def BFXILxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
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(ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
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"bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
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Sched<[WriteALU, ReadALU]> {
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Sched<[WriteALU, ReadALU, ReadALU]> {
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// As above, no disassembler allowed.
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let isAsmParserOnly = 1;
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let Constraints = "$src = $Rd";
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@ -1407,7 +1407,7 @@ defm UBFIZ : A64I_bitfield_insert<0b10, "ubfiz">;
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def BFIwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
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(ins GPR32:$src, GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),
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"bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
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Sched<[WriteALU, ReadALU]> {
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Sched<[WriteALU, ReadALU, ReadALU]> {
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// As above, no disassembler allowed.
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let isAsmParserOnly = 1;
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let Constraints = "$src = $Rd";
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@ -1416,7 +1416,7 @@ def BFIwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
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def BFIxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
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(ins GPR64:$src, GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),
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"bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
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Sched<[WriteALU, ReadALU]> {
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Sched<[WriteALU, ReadALU, ReadALU]> {
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// As above, no disassembler allowed.
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let isAsmParserOnly = 1;
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let Constraints = "$src = $Rd";
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@ -1560,7 +1560,8 @@ class A64I_condcmpregImpl<bit sf, bit op, RegisterClass GPR, string asmop>
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(outs),
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(ins GPR:$Rn, GPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond),
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!strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"),
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[], NoItinerary> {
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[], NoItinerary>,
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Sched<[WriteCMP, ReadCMP, ReadCMP]> {
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let Defs = [NZCV];
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}
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@ -1608,7 +1609,7 @@ multiclass A64I_condselSizes<bit op, bits<2> op2, string asmop,
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!strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"),
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[(set i32:$Rd, (select i32:$Rn, i32:$Rm))],
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NoItinerary>,
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Sched<[WriteCMP, ReadCMP]>;
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Sched<[WriteCMP, ReadCMP, ReadCMP]>;
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def xxxc : A64I_condsel<0b1, op, 0b0, op2,
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@ -1617,7 +1618,7 @@ multiclass A64I_condselSizes<bit op, bits<2> op2, string asmop,
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!strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"),
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[(set i64:$Rd, (select i64:$Rn, i64:$Rm))],
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NoItinerary>,
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Sched<[WriteCMP, ReadCMP]>;
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Sched<[WriteCMP, ReadCMP, ReadCMP]>;
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}
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}
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@ -1797,7 +1798,8 @@ multiclass dp_2src_crc<bit c, string asmop> {
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def X_wwx : A64I_dp_2src<0b1, {0, 1, 0, c, 1, 1}, 0b0,
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!strconcat(asmop, "x\t$Rd, $Rn, $Rm"),
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(outs GPR32:$Rd), (ins GPR32:$Rn, GPR64:$Rm), [],
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NoItinerary>;
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NoItinerary>,
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Sched<[WriteALU, ReadALU, ReadALU]>;
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}
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multiclass dp_2src_zext <bits<6> opcode, string asmop, SDPatternOperator op> {
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@ -2630,7 +2632,7 @@ let mayLoad = 1 in {
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(outs), (ins prefetch_op:$Rt, ldrlit_label:$Imm19),
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"prfm\t$Rt, $Imm19",
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[], NoItinerary>,
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Sched<[WriteLd]>;
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Sched<[WriteLd, ReadLd]>;
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}
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//===----------------------------------------------------------------------===//
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@ -2685,19 +2687,23 @@ class A64I_SRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
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multiclass A64I_SRex<string asmstr, bits<3> opcode, string prefix> {
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def _byte: A64I_SRexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
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(outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
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[], NoItinerary>;
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[], NoItinerary>,
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Sched<[WriteSt, ReadSt, ReadSt]>;
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def _hword: A64I_SRexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
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(outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
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[],NoItinerary>;
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[],NoItinerary>,
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Sched<[WriteSt, ReadSt, ReadSt]>;
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def _word: A64I_SRexs_impl<0b10, opcode, asmstr,
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(outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
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[], NoItinerary>;
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[], NoItinerary>,
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Sched<[WriteSt, ReadSt, ReadSt]>;
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def _dword: A64I_SRexs_impl<0b11, opcode, asmstr,
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(outs GPR32:$Rs), (ins GPR64:$Rt, GPR64xsp0:$Rn),
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[], NoItinerary>;
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[], NoItinerary>,
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Sched<[WriteSt, ReadSt, ReadSt]>;
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}
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defm STXR : A64I_SRex<"stxr", 0b000, "STXR">;
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@ -2792,22 +2798,26 @@ multiclass A64I_SLex<string asmstr, bits<3> opcode, string prefix> {
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def _byte: A64I_SLexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
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(outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
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[(atomic_store_release_8 i64:$Rn, i32:$Rt)],
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NoItinerary>;
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NoItinerary>,
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Sched<[WriteSt, ReadSt, ReadSt]>;
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def _hword: A64I_SLexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
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(outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
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[(atomic_store_release_16 i64:$Rn, i32:$Rt)],
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NoItinerary>;
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NoItinerary>,
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Sched<[WriteSt, ReadSt, ReadSt]>;
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def _word: A64I_SLexs_impl<0b10, opcode, asmstr,
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(outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
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[(atomic_store_release_32 i64:$Rn, i32:$Rt)],
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NoItinerary>;
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NoItinerary>,
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Sched<[WriteSt, ReadSt, ReadSt]>;
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def _dword: A64I_SLexs_impl<0b11, opcode, asmstr,
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(outs), (ins GPR64:$Rt, GPR64xsp0:$Rn),
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[(atomic_store_release_64 i64:$Rn, i64:$Rt)],
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NoItinerary>;
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NoItinerary>,
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Sched<[WriteSt, ReadSt, ReadSt]>;
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}
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defm STLR : A64I_SLex<"stlr", 0b101, "STLR">;
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@ -2832,12 +2842,14 @@ multiclass A64I_SPex<string asmstr, bits<3> opcode> {
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def _word: A64I_SPexs_impl<0b10, opcode, asmstr, (outs),
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(ins GPR32:$Rs, GPR32:$Rt, GPR32:$Rt2,
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GPR64xsp0:$Rn),
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[], NoItinerary>;
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[], NoItinerary>,
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Sched<[WriteSt, ReadSt, ReadSt, ReadSt]>;
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def _dword: A64I_SPexs_impl<0b11, opcode, asmstr, (outs),
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(ins GPR32:$Rs, GPR64:$Rt, GPR64:$Rt2,
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GPR64xsp0:$Rn),
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[], NoItinerary>;
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[], NoItinerary>,
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Sched<[WriteSt, ReadSt, ReadSt, ReadSt]>;
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}
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defm STXP : A64I_SPex<"stxp", 0b010>;
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@ -2865,13 +2877,13 @@ multiclass A64I_LPex<string asmstr, bits<3> opcode> {
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(outs GPR32:$Rt, GPR32:$Rt2),
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(ins GPR64xsp0:$Rn),
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[], NoItinerary>,
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Sched<[WriteLd]>;
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Sched<[WriteLd, WriteLd, ReadLd]>;
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def _dword: A64I_LPexs_impl<0b11, opcode, asmstr,
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(outs GPR64:$Rt, GPR64:$Rt2),
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(ins GPR64xsp0:$Rn),
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[], NoItinerary>,
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Sched<[WriteLd]>;
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Sched<[WriteLd, WriteLd, ReadLd]>;
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}
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defm LDXP : A64I_LPex<"ldxp", 0b010>;
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@ -3085,7 +3097,8 @@ multiclass A64I_LDRSTR_unsigned<string prefix, bits<2> size, bit v,
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def _STR : A64I_LSunsigimm<size, v, {high_opc, 0b0},
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(outs), (ins GPR:$Rt, GPR64xsp:$Rn, params.uimm12:$UImm12),
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"str" # asmsuffix # "\t$Rt, [$Rn, $UImm12]",
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[], NoItinerary> {
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[], NoItinerary>,
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Sched<[WriteSt, ReadSt, ReadSt]> {
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let mayStore = 1;
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}
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def : InstAlias<"str" # asmsuffix # " $Rt, [$Rn]",
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@ -3126,13 +3139,15 @@ multiclass A64I_LDRSTR_unsigned<string prefix, bits<2> size, bit v,
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(outs), (ins GPR:$Rt, GPR64xsp:$Rn, GPR32:$Rm,
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params.regextWm:$Ext),
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"str" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
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[], NoItinerary>;
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[], NoItinerary>,
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Sched<[WriteSt, ReadSt, ReadSt, ReadSt]>;
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def _Xm_RegOffset_STR : A64I_LSregoff<size, v, {high_opc, 0b0}, 0b1,
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(outs), (ins GPR:$Rt, GPR64xsp:$Rn, GPR64:$Rm,
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params.regextXm:$Ext),
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"str" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
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[], NoItinerary>;
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[], NoItinerary>,
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Sched<[WriteSt, ReadSt, ReadSt, ReadSt]>;
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}
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def : InstAlias<"str" # asmsuffix # " $Rt, [$Rn, $Rm]",
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(!cast<Instruction>(prefix # "_Xm_RegOffset_STR") GPR:$Rt, GPR64xsp:$Rn,
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@ -3142,7 +3157,8 @@ multiclass A64I_LDRSTR_unsigned<string prefix, bits<2> size, bit v,
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def _STUR : A64I_LSunalimm<size, v, {high_opc, 0b0},
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(outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
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"stur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
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[], NoItinerary> {
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[], NoItinerary>,
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Sched<[WriteSt, ReadSt, ReadSt]> {
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let mayStore = 1;
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}
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def : InstAlias<"stur" # asmsuffix # " $Rt, [$Rn]",
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@ -3163,7 +3179,8 @@ multiclass A64I_LDRSTR_unsigned<string prefix, bits<2> size, bit v,
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(outs GPR64xsp:$Rn_wb),
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(ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
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"str" # asmsuffix # "\t$Rt, [$Rn], $SImm9",
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[], NoItinerary> {
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[], NoItinerary>,
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Sched<[WriteSt, ReadSt, ReadSt]> {
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let Constraints = "$Rn = $Rn_wb";
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let mayStore = 1;
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@ -3176,7 +3193,7 @@ multiclass A64I_LDRSTR_unsigned<string prefix, bits<2> size, bit v,
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(ins GPR64xsp:$Rn, simm9:$SImm9),
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"ldr" # asmsuffix # "\t$Rt, [$Rn], $SImm9",
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[], NoItinerary>,
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Sched<[WriteLd, ReadLd]> {
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Sched<[WriteLd, WriteLd, ReadLd]> {
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let mayLoad = 1;
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let Constraints = "$Rn = $Rn_wb";
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let DecoderMethod = "DecodeSingleIndexedInstruction";
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@ -3187,7 +3204,8 @@ multiclass A64I_LDRSTR_unsigned<string prefix, bits<2> size, bit v,
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(outs GPR64xsp:$Rn_wb),
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(ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
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"str" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!",
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[], NoItinerary> {
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[], NoItinerary>,
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Sched<[WriteSt, ReadSt, ReadSt]> {
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let Constraints = "$Rn = $Rn_wb";
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let mayStore = 1;
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@ -3200,7 +3218,7 @@ multiclass A64I_LDRSTR_unsigned<string prefix, bits<2> size, bit v,
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(ins GPR64xsp:$Rn, simm9:$SImm9),
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"ldr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!",
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[], NoItinerary>,
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Sched<[WriteLd, ReadLd]> {
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Sched<[WriteLd, WriteLd, ReadLd]> {
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let mayLoad = 1;
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let Constraints = "$Rn = $Rn_wb";
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let DecoderMethod = "DecodeSingleIndexedInstruction";
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@ -3340,7 +3358,7 @@ multiclass A64I_LDR_signed<bits<2> size, string asmopcode, AddrParams params,
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(ins GPR64xsp:$Rn, simm9:$SImm9),
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"ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",
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[], NoItinerary>,
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Sched<[WriteLd, ReadLd]> {
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Sched<[WriteLd, WriteLd, ReadLd]> {
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let Constraints = "$Rn = $Rn_wb";
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let DecoderMethod = "DecodeSingleIndexedInstruction";
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}
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@ -3350,7 +3368,7 @@ multiclass A64I_LDR_signed<bits<2> size, string asmopcode, AddrParams params,
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(ins GPR64xsp:$Rn, simm9:$SImm9),
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"ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",
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[], NoItinerary>,
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Sched<[WriteLd, ReadLd]> {
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Sched<[WriteLd, WriteLd, ReadLd]> {
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let Constraints = "$Rn = $Rn_wb";
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let DecoderMethod = "DecodeSingleIndexedInstruction";
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}
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@ -3361,7 +3379,7 @@ multiclass A64I_LDR_signed<bits<2> size, string asmopcode, AddrParams params,
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(ins GPR64xsp:$Rn, simm9:$SImm9),
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"ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",
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[], NoItinerary>,
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Sched<[WriteLd, ReadLd]> {
|
||||
Sched<[WriteLd, WriteLd, ReadLd]> {
|
||||
let Constraints = "$Rn = $Rn_wb";
|
||||
let DecoderMethod = "DecodeSingleIndexedInstruction";
|
||||
}
|
||||
|
|
@ -3371,7 +3389,7 @@ multiclass A64I_LDR_signed<bits<2> size, string asmopcode, AddrParams params,
|
|||
(ins GPR64xsp:$Rn, simm9:$SImm9),
|
||||
"ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",
|
||||
[], NoItinerary>,
|
||||
Sched<[WriteLd, ReadLd]> {
|
||||
Sched<[WriteLd, WriteLd, ReadLd]> {
|
||||
let Constraints = "$Rn = $Rn_wb";
|
||||
let DecoderMethod = "DecodeSingleIndexedInstruction";
|
||||
}
|
||||
|
|
@ -3431,7 +3449,7 @@ def LDRSWx_PostInd
|
|||
(ins GPR64xsp:$Rn, simm9:$SImm9),
|
||||
"ldrsw\t$Rt, [$Rn], $SImm9",
|
||||
[], NoItinerary>,
|
||||
Sched<[WriteLd, ReadLd]> {
|
||||
Sched<[WriteLd, WriteLd, ReadLd]> {
|
||||
let mayLoad = 1;
|
||||
let Constraints = "$Rn = $Rn_wb";
|
||||
let DecoderMethod = "DecodeSingleIndexedInstruction";
|
||||
|
|
@ -3442,7 +3460,7 @@ def LDRSWx_PreInd : A64I_LSpreind<0b10, 0b0, 0b10,
|
|||
(ins GPR64xsp:$Rn, simm9:$SImm9),
|
||||
"ldrsw\t$Rt, [$Rn, $SImm9]!",
|
||||
[], NoItinerary>,
|
||||
Sched<[WriteLd, ReadLd]> {
|
||||
Sched<[WriteLd, WriteLd, ReadLd]> {
|
||||
let mayLoad = 1;
|
||||
let Constraints = "$Rn = $Rn_wb";
|
||||
let DecoderMethod = "DecodeSingleIndexedInstruction";
|
||||
|
|
@ -3652,7 +3670,7 @@ multiclass A64I_LSPsimple<bits<2> opc, bit v, RegisterClass SomeReg,
|
|||
(outs SomeReg:$Rt, SomeReg:$Rt2),
|
||||
(ins GPR64xsp:$Rn, simm7:$SImm7),
|
||||
"ldp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,
|
||||
Sched<[WriteLd, ReadLd]> {
|
||||
Sched<[WriteLd, WriteLd, ReadLd]> {
|
||||
let mayLoad = 1;
|
||||
let DecoderMethod = "DecodeLDSTPairInstruction";
|
||||
}
|
||||
|
|
@ -3666,7 +3684,8 @@ multiclass A64I_LSPsimple<bits<2> opc, bit v, RegisterClass SomeReg,
|
|||
GPR64xsp:$Rn,
|
||||
simm7:$SImm7),
|
||||
"stp\t$Rt, $Rt2, [$Rn], $SImm7",
|
||||
[], NoItinerary> {
|
||||
[], NoItinerary>,
|
||||
Sched<[WriteSt, ReadSt, ReadSt, ReadSt]> {
|
||||
let mayStore = 1;
|
||||
let Constraints = "$Rn = $Rn_wb";
|
||||
|
||||
|
|
@ -3679,16 +3698,17 @@ multiclass A64I_LSPsimple<bits<2> opc, bit v, RegisterClass SomeReg,
|
|||
(ins GPR64xsp:$Rn, simm7:$SImm7),
|
||||
"ldp\t$Rt, $Rt2, [$Rn], $SImm7",
|
||||
[], NoItinerary>,
|
||||
Sched<[WriteLd, ReadLd]> {
|
||||
Sched<[WriteLd, WriteLd, WriteLd, ReadLd]> {
|
||||
let mayLoad = 1;
|
||||
let Constraints = "$Rn = $Rn_wb";
|
||||
let DecoderMethod = "DecodeLDSTPairInstruction";
|
||||
}
|
||||
|
||||
def _PreInd_STR : A64I_LSPpreind<opc, v, 0b0, (outs GPR64xsp:$Rn_wb),
|
||||
(ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
|
||||
"stp\t$Rt, $Rt2, [$Rn, $SImm7]!",
|
||||
[], NoItinerary> {
|
||||
(ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
|
||||
"stp\t$Rt, $Rt2, [$Rn, $SImm7]!",
|
||||
[], NoItinerary>,
|
||||
Sched<[WriteSt, ReadSt, ReadSt, ReadSt]> {
|
||||
let mayStore = 1;
|
||||
let Constraints = "$Rn = $Rn_wb";
|
||||
let DecoderMethod = "DecodeLDSTPairInstruction";
|
||||
|
|
@ -3699,15 +3719,16 @@ multiclass A64I_LSPsimple<bits<2> opc, bit v, RegisterClass SomeReg,
|
|||
(ins GPR64xsp:$Rn, simm7:$SImm7),
|
||||
"ldp\t$Rt, $Rt2, [$Rn, $SImm7]!",
|
||||
[], NoItinerary>,
|
||||
Sched<[WriteLd, ReadLd]> {
|
||||
Sched<[WriteLd, WriteLd, WriteLd, ReadLd]> {
|
||||
let mayLoad = 1;
|
||||
let Constraints = "$Rn = $Rn_wb";
|
||||
let DecoderMethod = "DecodeLDSTPairInstruction";
|
||||
}
|
||||
|
||||
def _NonTemp_STR : A64I_LSPnontemp<opc, v, 0b0, (outs),
|
||||
(ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
|
||||
"stnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
|
||||
(ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
|
||||
"stnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,
|
||||
Sched<[WriteSt, ReadSt, ReadSt, ReadSt]> {
|
||||
let mayStore = 1;
|
||||
let DecoderMethod = "DecodeLDSTPairInstruction";
|
||||
}
|
||||
|
|
@ -3719,7 +3740,7 @@ multiclass A64I_LSPsimple<bits<2> opc, bit v, RegisterClass SomeReg,
|
|||
(outs SomeReg:$Rt, SomeReg:$Rt2),
|
||||
(ins GPR64xsp:$Rn, simm7:$SImm7),
|
||||
"ldnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,
|
||||
Sched<[WriteLd, ReadLd]> {
|
||||
Sched<[WriteLd, WriteLd, ReadLd]> {
|
||||
let mayLoad = 1;
|
||||
let DecoderMethod = "DecodeLDSTPairInstruction";
|
||||
}
|
||||
|
|
@ -3745,7 +3766,7 @@ def LDPSWx : A64I_LSPoffset<0b01, 0b0, 0b1,
|
|||
(outs GPR64:$Rt, GPR64:$Rt2),
|
||||
(ins GPR64xsp:$Rn, word_simm7:$SImm7),
|
||||
"ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,
|
||||
Sched<[WriteLd, ReadLd]> {
|
||||
Sched<[WriteLd, WriteLd, ReadLd]> {
|
||||
let mayLoad = 1;
|
||||
let DecoderMethod = "DecodeLDSTPairInstruction";
|
||||
}
|
||||
|
|
@ -3756,7 +3777,8 @@ def LDPSWx_PostInd : A64I_LSPpostind<0b01, 0b0, 0b1,
|
|||
(outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb),
|
||||
(ins GPR64xsp:$Rn, word_simm7:$SImm7),
|
||||
"ldpsw\t$Rt, $Rt2, [$Rn], $SImm7",
|
||||
[], NoItinerary> {
|
||||
[], NoItinerary>,
|
||||
Sched<[WriteLd, WriteLd, WriteLd, ReadLd]> {
|
||||
let mayLoad = 1;
|
||||
let Constraints = "$Rn = $Rn_wb";
|
||||
let DecoderMethod = "DecodeLDSTPairInstruction";
|
||||
|
|
@ -3767,7 +3789,7 @@ def LDPSWx_PreInd : A64I_LSPpreind<0b01, 0b0, 0b1,
|
|||
(ins GPR64xsp:$Rn, word_simm7:$SImm7),
|
||||
"ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]!",
|
||||
[], NoItinerary>,
|
||||
Sched<[WriteLd, ReadLd]> {
|
||||
Sched<[WriteLd, WriteLd, WriteLd, ReadLd]> {
|
||||
let mayLoad = 1;
|
||||
let Constraints = "$Rn = $Rn_wb";
|
||||
let DecoderMethod = "DecodeLDSTPairInstruction";
|
||||
|
|
@ -4150,7 +4172,8 @@ let isMoveImm = 1, isReMaterializable = 1,
|
|||
(ins movz64_imm:$FullImm)>;
|
||||
}
|
||||
|
||||
let Constraints = "$src = $Rd" in
|
||||
let Constraints = "$src = $Rd",
|
||||
SchedRW = [WriteALU, ReadALU] in
|
||||
defm MOVK : A64I_movwSizes<0b11, "movk",
|
||||
(ins GPR32:$src, movk32_imm:$FullImm),
|
||||
(ins GPR64:$src, movk64_imm:$FullImm)>;
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -37,8 +37,16 @@ def ReadDiv : SchedRead;
|
|||
// Loads
|
||||
def WriteLd : SchedWrite;
|
||||
def WritePreLd : SchedWrite;
|
||||
def WriteVecLd : SchedWrite;
|
||||
def ReadLd : SchedRead;
|
||||
def ReadPreLd : SchedRead;
|
||||
def ReadVecLd : SchedRead;
|
||||
|
||||
// Stores
|
||||
def WriteSt : SchedWrite;
|
||||
def WriteVecSt : SchedWrite;
|
||||
def ReadSt : SchedRead;
|
||||
def ReadVecSt : SchedRead;
|
||||
|
||||
// Branches
|
||||
def WriteBr : SchedWrite;
|
||||
|
|
|
|||
|
|
@ -71,9 +71,18 @@ def : WriteRes<WriteMAC, [A53UnitMAC]> { let Latency = 4; }
|
|||
// Div
|
||||
def : WriteRes<WriteDiv, [A53UnitDiv]> { let Latency = 4; }
|
||||
|
||||
// Load
|
||||
// Load - Note: Vector loads take 1-5 cycles to issue. For the WriteVecLd below,
|
||||
// choosing the median of 3 which makes the latency 6. May model this more
|
||||
// carefully in the future.
|
||||
def : WriteRes<WriteLd, [A53UnitLdSt]> { let Latency = 4; }
|
||||
def : WriteRes<WritePreLd, [A53UnitLdSt]> { let Latency = 4; }
|
||||
def : WriteRes<WriteVecLd, [A53UnitLdSt]> { let Latency = 6; }
|
||||
|
||||
// Store - Note: Vector stores take 1-3 cycles to issue. For the ReadVecSt below,
|
||||
// choosing the median of 2 which makes the latency 5. May model this more
|
||||
// carefully in the future.
|
||||
def : WriteRes<WriteSt, [A53UnitLdSt]> { let Latency = 4; }
|
||||
def : WriteRes<WriteVecSt, [A53UnitLdSt]> { let Latency = 5; }
|
||||
|
||||
// Branch
|
||||
def : WriteRes<WriteBr, [A53UnitB]>;
|
||||
|
|
@ -114,9 +123,14 @@ def : ReadAdvance<ReadMAC, 0>;
|
|||
// No forwarding defined for ReadDiv yet.
|
||||
def : ReadAdvance<ReadDiv, 0>;
|
||||
|
||||
// No forwarding defined for ReadLd, ReadPreLd yet.
|
||||
// No forwarding defined for ReadLd, ReadPreLd, ReadVecLd yet.
|
||||
def : ReadAdvance<ReadLd, 0>;
|
||||
def : ReadAdvance<ReadPreLd, 0>;
|
||||
def : ReadAdvance<ReadVecLd, 0>;
|
||||
|
||||
// No forwarding defined for ReadSt and ReadVecSt yet.
|
||||
def : ReadAdvance<ReadSt, 0>;
|
||||
def : ReadAdvance<ReadVecSt, 0>;
|
||||
|
||||
// No forwarding defined for ReadFPALU yet.
|
||||
def : ReadAdvance<ReadFPALU, 0>;
|
||||
|
|
|
|||
|
|
@ -4,13 +4,15 @@
|
|||
; The Cortex-A53 machine model will cause the MADD instruction to be scheduled
|
||||
; much higher than the ADD instructions in order to hide latency. When not
|
||||
; specifying a subtarget, the MADD will remain near the end of the block.
|
||||
;
|
||||
; CHECK: ********** MI Scheduling **********
|
||||
; CHECK: main
|
||||
; CHECK: *** Final schedule for BB#2 ***
|
||||
; CHECK: SU(13)
|
||||
; CHECK: MADDwwww
|
||||
; CHECK: SU(4)
|
||||
; CHECK: ADDwwi_lsl0_s
|
||||
; CHECK: ********** MI Scheduling **********
|
||||
; CHECK: ********** INTERVALS **********
|
||||
@main.x = private unnamed_addr constant [8 x i32] [i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1], align 4
|
||||
@main.y = private unnamed_addr constant [8 x i32] [i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2], align 4
|
||||
|
||||
|
|
@ -76,6 +78,33 @@ for.end: ; preds = %for.cond
|
|||
ret i32 %add6
|
||||
}
|
||||
|
||||
|
||||
; The Cortex-A53 machine model will cause the FDIVvvv_42 to be raised to
|
||||
; hide latency. Whereas normally there would only be a single FADDvvv_4s
|
||||
; after it, this test checks to make sure there are more than one.
|
||||
;
|
||||
; CHECK: ********** MI Scheduling **********
|
||||
; CHECK: neon4xfloat:BB#0
|
||||
; CHECK: *** Final schedule for BB#0 ***
|
||||
; CHECK: FDIVvvv_4S
|
||||
; CHECK: FADDvvv_4S
|
||||
; CHECK: FADDvvv_4S
|
||||
; CHECK: ********** INTERVALS **********
|
||||
define <4 x float> @neon4xfloat(<4 x float> %A, <4 x float> %B) {
|
||||
%tmp1 = fadd <4 x float> %A, %B;
|
||||
%tmp2 = fadd <4 x float> %A, %tmp1;
|
||||
%tmp3 = fadd <4 x float> %A, %tmp2;
|
||||
%tmp4 = fadd <4 x float> %A, %tmp3;
|
||||
%tmp5 = fadd <4 x float> %A, %tmp4;
|
||||
%tmp6 = fadd <4 x float> %A, %tmp5;
|
||||
%tmp7 = fadd <4 x float> %A, %tmp6;
|
||||
%tmp8 = fadd <4 x float> %A, %tmp7;
|
||||
%tmp9 = fdiv <4 x float> %A, %B;
|
||||
%tmp10 = fadd <4 x float> %tmp8, %tmp9;
|
||||
|
||||
ret <4 x float> %tmp10
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #1
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user