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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-09-24 23:28:41 +00:00
Remove filtering concept from X86 disassembler table generation. It's no longer necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201299 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -208,6 +208,17 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
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}
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}
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if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) {
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ShouldBeEmitted = false;
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return;
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}
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// Special case since there is no attribute class for 64-bit and VEX
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if (Name == "VMASKMOVDQU64") {
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ShouldBeEmitted = false;
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return;
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}
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ShouldBeEmitted = true;
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}
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@@ -221,10 +232,10 @@ void RecognizableInstr::processInstr(DisassemblerTables &tables,
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RecognizableInstr recogInstr(tables, insn, uid);
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recogInstr.emitInstructionSpecifier();
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if (recogInstr.shouldBeEmitted())
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if (recogInstr.shouldBeEmitted()) {
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recogInstr.emitInstructionSpecifier();
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recogInstr.emitDecodePath(tables);
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}
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}
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#define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
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@@ -380,36 +391,6 @@ InstructionContext RecognizableInstr::insnContext() const {
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return insnContext;
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}
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RecognizableInstr::filter_ret RecognizableInstr::filter() const {
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///////////////////
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// FILTER_STRONG
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//
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// Filter out intrinsics
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assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
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if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble))
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return FILTER_STRONG;
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// Filter out artificial instructions but leave in the LOCK_PREFIX so it is
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// printed as a separate "instruction".
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/////////////////
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// FILTER_WEAK
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//
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// Special cases.
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if (Name == "VMASKMOVDQU64")
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return FILTER_WEAK;
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return FILTER_NORMAL;
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}
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void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
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unsigned &physicalOperandIndex,
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unsigned &numPhysicalOperands,
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@@ -445,20 +426,6 @@ void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
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void RecognizableInstr::emitInstructionSpecifier() {
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Spec->name = Name;
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if (!ShouldBeEmitted)
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return;
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switch (filter()) {
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case FILTER_WEAK:
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Spec->filtered = true;
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break;
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case FILTER_STRONG:
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ShouldBeEmitted = false;
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return;
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case FILTER_NORMAL:
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break;
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}
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Spec->insnContext = insnContext();
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const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
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