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Fix a recent regression. ClrOpcode is not set for i8; for i8, if

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we want to clear %ah to zero before a division, just use a
zero-extending mov to %al. This fixes PR3366.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62691 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2009-01-21 14:50:16 +00:00
parent 1421b7bc23
commit 1ef4d8f7ee
2 changed files with 24 additions and 2 deletions
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5
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -1381,9 +1381,10 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
SDValue Tmp0, Tmp1, Tmp2, Tmp3;
bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
bool signBitIsZero = CurDAG->SignBitIsZero(N0);
SDValue InFlag;
if (NVT == MVT::i8 && !isSigned) {
if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
// Special case for div8, just use a move with zero extension to AX to
// clear the upper 8 bits (AH).
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Move, Chain;
@ -1405,7 +1406,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
InFlag =
CurDAG->getCopyToReg(CurDAG->getEntryNode(),
LoReg, N0, SDValue()).getValue(1);
if (isSigned && !CurDAG->SignBitIsZero(N0)) {
if (isSigned && !signBitIsZero) {
// Sign extend the low part into the high part.
InFlag =
SDValue(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0);

21
test/CodeGen/X86/pr3366.ll Normal file
View File

@ -0,0 +1,21 @@
; RUN: llvm-as < %s | llc -march=x86 | grep movzbl
; PR3366
define void @_ada_c34002a() nounwind {
entry:
%0 = load i8* null, align 1
%1 = sdiv i8 90, %0
%2 = icmp ne i8 %1, 3
%3 = zext i1 %2 to i8
%toBool449 = icmp ne i8 %3, 0
%4 = or i1 false, %toBool449
%5 = zext i1 %4 to i8
%toBool450 = icmp ne i8 %5, 0
br i1 %toBool450, label %bb451, label %bb457
bb451:
br label %bb457
bb457:
unreachable
}