mirror of
https://github.com/c64scene-ar/llvm-6502.git
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[mips] Add the capability to search delay slot filling instructions in
successor basic blocks. Currently this is off by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176329 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
888e8fefd2
commit
1f0aca857b
@ -14,12 +14,14 @@
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#define DEBUG_TYPE "delay-slot-filler"
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#include "Mips.h"
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#include "MipsInstrInfo.h"
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#include "MipsTargetMachine.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Analysis/ValueTracking.h"
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#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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@ -66,6 +68,24 @@ static cl::opt<bool> DisableBackwardSearch(
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cl::Hidden);
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namespace {
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typedef MachineBasicBlock::iterator Iter;
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typedef MachineBasicBlock::reverse_iterator ReverseIter;
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typedef SmallDenseMap<MachineBasicBlock*, MachineInstr*, 2> BB2BrMap;
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/// \brief A functor comparing edge weight of two blocks.
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struct CmpWeight {
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CmpWeight(const MachineBasicBlock &S,
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const MachineBranchProbabilityInfo &P) : Src(S), Prob(P) {}
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bool operator()(const MachineBasicBlock *Dst0,
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const MachineBasicBlock *Dst1) const {
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return Prob.getEdgeWeight(&Src, Dst0) < Prob.getEdgeWeight(&Src, Dst1);
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}
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const MachineBasicBlock &Src;
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const MachineBranchProbabilityInfo &Prob;
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};
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class RegDefsUses {
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public:
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RegDefsUses(TargetMachine &TM);
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@ -74,6 +94,14 @@ namespace {
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/// This function sets all caller-saved registers in Defs.
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void setCallerSaved(const MachineInstr &MI);
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/// This function sets all unallocatable registers in Defs.
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void setUnallocatableRegs(const MachineFunction &MF);
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/// Set bits in Uses corresponding to MBB's live-out registers except for
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/// the registers that are live-in to SuccBB.
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void addLiveOut(const MachineBasicBlock &MBB,
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const MachineBasicBlock &SuccBB);
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bool update(const MachineInstr &MI, unsigned Begin, unsigned End);
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private:
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@ -90,14 +118,41 @@ namespace {
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/// Base class for inspecting loads and stores.
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class InspectMemInstr {
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public:
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virtual bool hasHazard(const MachineInstr &MI) = 0;
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InspectMemInstr(bool ForbidMemInstr_)
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: OrigSeenLoad(false), OrigSeenStore(false), SeenLoad(false),
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SeenStore(false), ForbidMemInstr(ForbidMemInstr_) {}
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/// Return true if MI cannot be moved to delay slot.
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bool hasHazard(const MachineInstr &MI);
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virtual ~InspectMemInstr() {}
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protected:
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/// Flags indicating whether loads or stores have been seen.
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bool OrigSeenLoad, OrigSeenStore, SeenLoad, SeenStore;
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/// Memory instructions are not allowed to move to delay slot if this flag
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/// is true.
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bool ForbidMemInstr;
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private:
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virtual bool hasHazard_(const MachineInstr &MI) = 0;
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};
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/// This subclass rejects any memory instructions.
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class NoMemInstr : public InspectMemInstr {
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public:
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virtual bool hasHazard(const MachineInstr &MI);
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NoMemInstr() : InspectMemInstr(true) {}
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private:
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virtual bool hasHazard_(const MachineInstr &MI) { return true; }
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};
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/// This subclass accepts loads from stacks and constant loads.
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class LoadFromStackOrConst : public InspectMemInstr {
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public:
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LoadFromStackOrConst() : InspectMemInstr(false) {}
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private:
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virtual bool hasHazard_(const MachineInstr &MI);
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};
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/// This subclass uses memory dependence information to determine whether a
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@ -106,10 +161,9 @@ namespace {
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public:
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MemDefsUses(const MachineFrameInfo *MFI);
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/// Return true if MI cannot be moved to delay slot.
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virtual bool hasHazard(const MachineInstr &MI);
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private:
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virtual bool hasHazard_(const MachineInstr &MI);
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/// Update Defs and Uses. Return true if there exist dependences that
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/// disqualify the delay slot candidate between V and values in Uses and Defs.
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bool updateDefsUses(const Value *V, bool MayStore);
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@ -121,16 +175,9 @@ namespace {
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const MachineFrameInfo *MFI;
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SmallPtrSet<const Value*, 4> Uses, Defs;
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/// Flags indicating whether loads or stores have been seen.
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bool SeenLoad, SeenStore;
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/// Flags indicating whether loads or stores with no underlying objects have
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/// been seen.
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bool SeenNoObjLoad, SeenNoObjStore;
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/// Memory instructions are not allowed to move to delay slot if this flag
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/// is true.
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bool ForbidMemInstr;
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};
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class Filler : public MachineFunctionPass {
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@ -153,10 +200,12 @@ namespace {
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return Changed;
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}
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private:
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typedef MachineBasicBlock::iterator Iter;
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typedef MachineBasicBlock::reverse_iterator ReverseIter;
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void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<MachineBranchProbabilityInfo>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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private:
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bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
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/// This function checks if it is valid to move Candidate to the delay slot
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@ -179,6 +228,26 @@ namespace {
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/// that can be moved to the delay slot. Returns true on success.
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bool searchForward(MachineBasicBlock &MBB, Iter Slot) const;
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/// This function searches MBB's successor blocks for an instruction that
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/// can be moved to the delay slot and inserts clones of the instruction into
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/// the successor blocks.
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bool searchSuccBBs(MachineBasicBlock &MBB, Iter Slot) const;
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/// Pick a successor block of MBB. Return NULL if MBB doesn't have a successor
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/// block that is not a landing pad.
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MachineBasicBlock *selectSuccBB(MachineBasicBlock &B) const;
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/// This function analyzes MBB and returns an instruction with an unoccupied
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/// slot that branches to Dst.
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std::pair<MipsInstrInfo::BranchType, MachineInstr *>
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getBranch(MachineBasicBlock &MBB, const MachineBasicBlock &Dst) const;
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/// Examine Pred and see if it is possible to insert an instruction into
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/// one of its branches delay slot or its end.
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bool examinePred(MachineBasicBlock &Pred, const MachineBasicBlock &Succ,
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RegDefsUses &RegDU, bool &HasMultipleSuccs,
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BB2BrMap &BrMap) const;
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bool terminateSearch(const MachineInstr &Candidate) const;
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TargetMachine &TM;
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@ -189,6 +258,45 @@ namespace {
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char Filler::ID = 0;
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} // end of anonymous namespace
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static bool hasUnoccupiedSlot(const MachineInstr *MI) {
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return MI->hasDelaySlot() && !MI->isBundledWithSucc();
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}
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/// This function inserts clones of Filler into predecessor blocks.
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static void insertDelayFiller(Iter Filler, const BB2BrMap &BrMap) {
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MachineFunction *MF = Filler->getParent()->getParent();
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for (BB2BrMap::const_iterator I = BrMap.begin(); I != BrMap.end(); ++I) {
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if (I->second) {
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MIBundleBuilder(I->second).append(MF->CloneMachineInstr(&*Filler));
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++UsefulSlots;
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} else {
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I->first->insert(I->first->end(), MF->CloneMachineInstr(&*Filler));
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}
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}
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}
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/// This function adds registers Filler defines to MBB's live-in register list.
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static void addLiveInRegs(Iter Filler, MachineBasicBlock &MBB) {
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for (unsigned I = 0, E = Filler->getNumOperands(); I != E; ++I) {
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const MachineOperand &MO = Filler->getOperand(I);
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unsigned R;
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if (!MO.isReg() || !MO.isDef() || !(R = MO.getReg()))
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continue;
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#ifndef NDEBUG
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const MachineFunction &MF = *MBB.getParent();
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assert(MF.getTarget().getRegisterInfo()->getAllocatableSet(MF).test(R) &&
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"Shouldn't move an instruction with unallocatable registers across "
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"basic block boundaries.");
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#endif
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if (!MBB.isLiveIn(R))
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MBB.addLiveIn(R);
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}
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}
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RegDefsUses::RegDefsUses(TargetMachine &TM)
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: TRI(*TM.getRegisterInfo()), Defs(TRI.getNumRegs(), false),
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Uses(TRI.getNumRegs(), false) {}
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@ -226,6 +334,29 @@ void RegDefsUses::setCallerSaved(const MachineInstr &MI) {
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Defs |= CallerSavedRegs;
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}
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void RegDefsUses::setUnallocatableRegs(const MachineFunction &MF) {
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BitVector AllocSet = TRI.getAllocatableSet(MF);
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for (int R = AllocSet.find_first(); R != -1; R = AllocSet.find_next(R))
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for (MCRegAliasIterator AI(R, &TRI, false); AI.isValid(); ++AI)
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AllocSet.set(*AI);
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AllocSet.set(Mips::ZERO);
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AllocSet.set(Mips::ZERO_64);
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Defs |= AllocSet.flip();
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}
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void RegDefsUses::addLiveOut(const MachineBasicBlock &MBB,
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const MachineBasicBlock &SuccBB) {
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for (MachineBasicBlock::const_succ_iterator SI = MBB.succ_begin(),
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SE = MBB.succ_end(); SI != SE; ++SI)
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if (*SI != &SuccBB)
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for (MachineBasicBlock::livein_iterator LI = (*SI)->livein_begin(),
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LE = (*SI)->livein_end(); LI != LE; ++LI)
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Uses.set(*LI);
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}
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bool RegDefsUses::update(const MachineInstr &MI, unsigned Begin, unsigned End) {
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BitVector NewDefs(TRI.getNumRegs()), NewUses(TRI.getNumRegs());
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bool HasHazard = false;
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@ -264,24 +395,15 @@ bool RegDefsUses::isRegInSet(const BitVector &RegSet, unsigned Reg) const {
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return false;
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}
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bool NoMemInstr::hasHazard(const MachineInstr &MI) {
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// Return true if MI accesses memory.
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return (MI.mayStore() || MI.mayLoad());
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}
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MemDefsUses::MemDefsUses(const MachineFrameInfo *MFI_)
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: MFI(MFI_), SeenLoad(false), SeenStore(false), SeenNoObjLoad(false),
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SeenNoObjStore(false), ForbidMemInstr(false) {}
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bool MemDefsUses::hasHazard(const MachineInstr &MI) {
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bool InspectMemInstr::hasHazard(const MachineInstr &MI) {
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if (!MI.mayStore() && !MI.mayLoad())
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return false;
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if (ForbidMemInstr)
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return true;
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bool OrigSeenLoad = SeenLoad, OrigSeenStore = SeenStore;
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OrigSeenLoad = SeenLoad;
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OrigSeenStore = SeenStore;
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SeenLoad |= MI.mayLoad();
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SeenStore |= MI.mayStore();
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@ -292,6 +414,33 @@ bool MemDefsUses::hasHazard(const MachineInstr &MI) {
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return true;
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}
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return hasHazard_(MI);
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}
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bool LoadFromStackOrConst::hasHazard_(const MachineInstr &MI) {
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if (MI.mayStore())
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return true;
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if (!MI.hasOneMemOperand() || !(*MI.memoperands_begin())->getValue())
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return true;
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const Value *V = (*MI.memoperands_begin())->getValue();
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if (isa<FixedStackPseudoSourceValue>(V))
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return false;
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if (const PseudoSourceValue *PSV = dyn_cast<const PseudoSourceValue>(V))
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return !PSV->PseudoSourceValue::isConstant(0) &&
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(V != PseudoSourceValue::getStack());
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return true;
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}
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MemDefsUses::MemDefsUses(const MachineFrameInfo *MFI_)
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: InspectMemInstr(false), MFI(MFI_), SeenNoObjLoad(false),
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SeenNoObjStore(false) {}
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bool MemDefsUses::hasHazard_(const MachineInstr &MI) {
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bool HasHazard = false;
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SmallVector<const Value *, 4> Objs;
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@ -353,16 +502,24 @@ bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
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bool Changed = false;
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for (Iter I = MBB.begin(); I != MBB.end(); ++I) {
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if (!I->hasDelaySlot())
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if (!hasUnoccupiedSlot(&*I))
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continue;
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++FilledSlots;
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Changed = true;
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// Delay slot filling is disabled at -O0.
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if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None) &&
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(searchBackward(MBB, I) || searchForward(MBB, I)))
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continue;
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if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None)) {
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if (searchBackward(MBB, I))
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continue;
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if (I->isTerminator()) {
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if (searchSuccBBs(MBB, I))
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continue;
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} else if (searchForward(MBB, I)) {
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continue;
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}
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}
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// Bundle the NOP to the instruction with the delay slot.
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BuildMI(MBB, llvm::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
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@ -404,6 +561,9 @@ bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
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}
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bool Filler::searchBackward(MachineBasicBlock &MBB, Iter Slot) const {
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if (DisableBackwardSearch)
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return false;
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RegDefsUses RegDU(TM);
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MemDefsUses MemDU(MBB.getParent()->getFrameInfo());
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ReverseIter Filler;
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@ -422,7 +582,7 @@ bool Filler::searchBackward(MachineBasicBlock &MBB, Iter Slot) const {
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bool Filler::searchForward(MachineBasicBlock &MBB, Iter Slot) const {
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// Can handle only calls.
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if (!Slot->isCall())
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if (DisableForwardSearch || !Slot->isCall())
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return false;
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RegDefsUses RegDU(TM);
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@ -441,6 +601,117 @@ bool Filler::searchForward(MachineBasicBlock &MBB, Iter Slot) const {
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return false;
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}
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bool Filler::searchSuccBBs(MachineBasicBlock &MBB, Iter Slot) const {
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if (DisableSuccBBSearch)
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return false;
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MachineBasicBlock *SuccBB = selectSuccBB(MBB);
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if (!SuccBB)
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return false;
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RegDefsUses RegDU(TM);
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bool HasMultipleSuccs = false;
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BB2BrMap BrMap;
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OwningPtr<InspectMemInstr> IM;
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Iter Filler;
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// Iterate over SuccBB's predecessor list.
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for (MachineBasicBlock::pred_iterator PI = SuccBB->pred_begin(),
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PE = SuccBB->pred_end(); PI != PE; ++PI)
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if (!examinePred(**PI, *SuccBB, RegDU, HasMultipleSuccs, BrMap))
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return false;
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// Do not allow moving instructions which have unallocatable register operands
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// across basic block boundaries.
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RegDU.setUnallocatableRegs(*MBB.getParent());
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// Only allow moving loads from stack or constants if any of the SuccBB's
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// predecessors have multiple successors.
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if (HasMultipleSuccs) {
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IM.reset(new LoadFromStackOrConst());
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} else {
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const MachineFrameInfo *MFI = MBB.getParent()->getFrameInfo();
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IM.reset(new MemDefsUses(MFI));
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}
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if (!searchRange(MBB, SuccBB->begin(), SuccBB->end(), RegDU, *IM, Filler))
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return false;
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insertDelayFiller(Filler, BrMap);
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addLiveInRegs(Filler, *SuccBB);
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Filler->eraseFromParent();
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return true;
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}
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MachineBasicBlock *Filler::selectSuccBB(MachineBasicBlock &B) const {
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if (B.succ_empty())
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return NULL;
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// Select the successor with the larget edge weight.
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CmpWeight Cmp(B, getAnalysis<MachineBranchProbabilityInfo>());
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MachineBasicBlock *S = *std::max_element(B.succ_begin(), B.succ_end(), Cmp);
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return S->isLandingPad() ? NULL : S;
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}
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std::pair<MipsInstrInfo::BranchType, MachineInstr *>
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Filler::getBranch(MachineBasicBlock &MBB, const MachineBasicBlock &Dst) const {
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const MipsInstrInfo *TII =
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static_cast<const MipsInstrInfo*>(TM.getInstrInfo());
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MachineBasicBlock *TrueBB = 0, *FalseBB = 0;
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SmallVector<MachineInstr*, 2> BranchInstrs;
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SmallVector<MachineOperand, 2> Cond;
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MipsInstrInfo::BranchType R =
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TII->AnalyzeBranch(MBB, TrueBB, FalseBB, Cond, false, BranchInstrs);
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if ((R == MipsInstrInfo::BT_None) || (R == MipsInstrInfo::BT_NoBranch))
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return std::make_pair(R, (MachineInstr*)NULL);
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if (R != MipsInstrInfo::BT_CondUncond) {
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if (!hasUnoccupiedSlot(BranchInstrs[0]))
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return std::make_pair(MipsInstrInfo::BT_None, (MachineInstr*)NULL);
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assert(((R != MipsInstrInfo::BT_Uncond) || (TrueBB == &Dst)));
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return std::make_pair(R, BranchInstrs[0]);
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}
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assert((TrueBB == &Dst) || (FalseBB == &Dst));
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// Examine the conditional branch. See if its slot is occupied.
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if (hasUnoccupiedSlot(BranchInstrs[0]))
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return std::make_pair(MipsInstrInfo::BT_Cond, BranchInstrs[0]);
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// If that fails, try the unconditional branch.
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if (hasUnoccupiedSlot(BranchInstrs[1]) && (FalseBB == &Dst))
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return std::make_pair(MipsInstrInfo::BT_Uncond, BranchInstrs[1]);
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return std::make_pair(MipsInstrInfo::BT_None, (MachineInstr*)NULL);
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}
|
||||
|
||||
bool Filler::examinePred(MachineBasicBlock &Pred, const MachineBasicBlock &Succ,
|
||||
RegDefsUses &RegDU, bool &HasMultipleSuccs,
|
||||
BB2BrMap &BrMap) const {
|
||||
std::pair<MipsInstrInfo::BranchType, MachineInstr *> P =
|
||||
getBranch(Pred, Succ);
|
||||
|
||||
// Return if either getBranch wasn't able to analyze the branches or there
|
||||
// were no branches with unoccupied slots.
|
||||
if (P.first == MipsInstrInfo::BT_None)
|
||||
return false;
|
||||
|
||||
if ((P.first != MipsInstrInfo::BT_Uncond) &&
|
||||
(P.first != MipsInstrInfo::BT_NoBranch)) {
|
||||
HasMultipleSuccs = true;
|
||||
RegDU.addLiveOut(Pred, Succ);
|
||||
}
|
||||
|
||||
BrMap[&Pred] = P.second;
|
||||
return true;
|
||||
}
|
||||
|
||||
bool Filler::delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU,
|
||||
InspectMemInstr &IM) const {
|
||||
bool HasHazard = (Candidate.isImplicitDef() || Candidate.isKill());
|
||||
|
||||
@ -4,6 +4,9 @@
|
||||
; RUN: FileCheck %s -check-prefix=STATICO1
|
||||
; RUN: llc -march=mipsel -disable-mips-df-forward-search=false \
|
||||
; RUN: -relocation-model=static < %s | FileCheck %s -check-prefix=FORWARD
|
||||
; RUN: llc -march=mipsel -disable-mips-df-backward-search \
|
||||
; RUN: -disable-mips-df-succbb-search=false < %s | \
|
||||
; RUN: FileCheck %s -check-prefix=SUCCBB
|
||||
|
||||
define void @foo1() nounwind {
|
||||
entry:
|
||||
@ -75,6 +78,7 @@ if.end:
|
||||
;
|
||||
; Default: foo6:
|
||||
; Default-NOT: nop
|
||||
; Default: .end foo6
|
||||
|
||||
define void @foo6(float %a0, double %a1) nounwind {
|
||||
entry:
|
||||
@ -109,6 +113,7 @@ entry:
|
||||
; FORWARD: jal foo11
|
||||
; FORWARD: jal foo11
|
||||
; FORWARD-NOT: nop
|
||||
; FORWARD: end foo10
|
||||
|
||||
define void @foo10() nounwind {
|
||||
entry:
|
||||
@ -121,3 +126,54 @@ entry:
|
||||
}
|
||||
|
||||
declare void @foo11()
|
||||
|
||||
; Check that delay slots of branches in both the entry block and loop body are
|
||||
; filled.
|
||||
;
|
||||
; SUCCBB: succbbs_loop1:
|
||||
; SUCCBB: bne ${{[0-9]+}}, $zero, $BB
|
||||
; SUCCBB-NEXT: addiu
|
||||
; SUCCBB: bne ${{[0-9]+}}, $zero, $BB
|
||||
; SUCCBB-NEXT: addiu
|
||||
|
||||
define i32 @succbbs_loop1(i32* nocapture %a, i32 %n) {
|
||||
entry:
|
||||
%cmp4 = icmp sgt i32 %n, 0
|
||||
br i1 %cmp4, label %for.body, label %for.end
|
||||
|
||||
for.body: ; preds = %entry, %for.body
|
||||
%s.06 = phi i32 [ %add, %for.body ], [ 0, %entry ]
|
||||
%i.05 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
|
||||
%arrayidx = getelementptr inbounds i32* %a, i32 %i.05
|
||||
%0 = load i32* %arrayidx, align 4
|
||||
%add = add nsw i32 %0, %s.06
|
||||
%inc = add nsw i32 %i.05, 1
|
||||
%exitcond = icmp eq i32 %inc, %n
|
||||
br i1 %exitcond, label %for.end, label %for.body
|
||||
|
||||
for.end: ; preds = %for.body, %entry
|
||||
%s.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.body ]
|
||||
ret i32 %s.0.lcssa
|
||||
}
|
||||
|
||||
; Check that the first branch has its slot filled.
|
||||
;
|
||||
; SUCCBB: succbbs_br1:
|
||||
; SUCCBB: beq ${{[0-9]+}}, $zero, $BB
|
||||
; SUCCBB-NEXT: lw $25, %call16(foo100)
|
||||
|
||||
define void @succbbs_br1(i32 %a) {
|
||||
entry:
|
||||
%tobool = icmp eq i32 %a, 0
|
||||
br i1 %tobool, label %if.end, label %if.then
|
||||
|
||||
if.then: ; preds = %entry
|
||||
tail call void @foo100() #1
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %entry, %if.then
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @foo100()
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user